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The global semiconductor market dropped 8.7% in 1st quarter 2023 versus 4th quarter 2022, according to WSTS. This was the steepest quarter-to-quarter decline since a 14.7% drop in 1Q 2019. 1Q 2023 was down 21.3% from a year earlier, the largest year-to-year decline in thirteen years since a 30.4% drop in 1Q 2009. Revenues of the top fifteen semiconductor companies reflect this weakness, with a weighted average revenue decline of 12% in 1Q 2023 from 4Q 2022.
The hardest hit were the memory companies (Samsung, SK Hynix, and Micron Technology) which collectively dropped 26%. The sharpest falloffs of the non-memory companies were Intel (down 17%) and MediaTek (down 12%). Collectively, the 12 non-memory companies declined 7%. Four companies managed revenue gains in 1Q23 versus 4Q22. Nvidia has not reported its equivalent 1Q23 revenues, but its guidance from the prior quarter was a 7.4% gain. Qualcomm, Infineon, and Analog Devices also grew their revenues.
Comparing 1Q 2023 revenue rankings versus 4Q 2022, Intel is again number one after Samsung’s revenues dropped 32% in 1Q23. Broadcom and Qualcomm remain numbers 3 and 4, respectively. SK Hynix dropped from number 5 in 4Q22 to number 10 in 1Q23 with a 34% revenue decline. Nvidia and AMD each moved up a spot to 5 and 6. Infineon Technologies became number 7, passing Texas Instruments (TI) and STMicroelectronics which remain 8 and 9. Micron Technology remains number 11. Analog Devices rose two spots to number 12, with MediaTek and NXP Semiconductors slipping from 12 and 13 to 13 and 14. Kioxia dropped out of the top 15 with a 26% percent decline. Renesas Electronics entered the rankings at number 15.
We at Semiconductor Intelligence define semiconductor suppliers using the WSTS methodology. Only final sellers of semiconductors are included. Thus, foundries such as TSMC are not included since they generally sell their output to other semiconductor companies which are the final seller. This avoids double counting revenues. Also, companies which use semiconductors only in their own products, such as Apple, are not included.
The guidance for 2Q 2023 revenues versus 1Q 2023 is mixed. Of the 11 companies providing guidance, five expect increases and six expect decreases. The largest expected gains are 2.5% from NXP and 2.4% from Intel. Qualcomm has the largest expected decline at 9.3%. Weak end demand and continuing inventory adjustments in the channel are cited by many companies as factors in the cautious outlook. Automotive and industrial remain the bright spots, with five companies citing these sectors as growing or at least flat versus the prior quarter. The uncertainty of 2Q 2023 is reflected by the range of revenue guidance. The weighted average guidance for 2Q23 is a 1% decline from 1Q23. However, the weighted average high-end guidance is a 3% increase while the weighted average low-end guidance is a 5% decline, an 8 percentage-point difference.
As reported in the Semiconductor Intelligence April newsletter, shipments of the key end equipment were down sharply in 1Q 2023. IDC estimated PC shipments were down 29% from a year ago. Recent IDC estimates of 1Q 2023 smartphone shipments show a 14.6% drop from a year ago. Continuing inventory adjustments throughout the channel indicate semiconductor shipments will lag end equipment shipments. Once inventories return to target levels, they are likely to remain lean as end equipment makers will be reluctant to build inventories with the uncertain economic outlook.
Forecasts for the 2023 semiconductor market released within the last month range from a 20% drop from Future Horizons to an 11.2% drop from Gartner. Our latest forecast from Semiconductor Intelligence calls for a 15% decline. Given the weakness in 1Q 2023 and the cautious outlook for 2Q 2023, a double-digit fall-off for year 2023 is almost certain.
The growth rate of the semiconductor market in 2024 depends on the timing of the market recovery in 2023. Gartner’s May projection was an 18.5% gain in 2024, assuming a 70% increase in the memory market. We at Semiconductor Intelligence are more cautious. Our baseline forecast for 2024 is 9% growth. Our 2024 forecast range is from 3% to 15%.
Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.
Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com
Dan is joined by Hal Conklin, Vice President of Business Development for Lightelligence. Hal is an experienced strategic leader in the technology industry. Prior to joining Lightelligence, he spent 10 years at Arm and he also worked in executive management roles at several start-ups.
Hal provides details of a new and ground-breaking way to use light to address computing challenges as well as communication challenges. He outlines the substantial performance gains and power reduction that are possible with this new approach and details where it can be applied. You can learn more about the company at www.lightelligence.ai.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
The SPIE Advanced Lithography Conference was held in February. I recently had the opportunity to interview Steven Scheer, vice president of advanced patterning process and materials at imec and review selected papers that imec presented.
I asked Steve what the overarching message was at SPIE this year, he said readiness for High NA is key. He identified three key ecosystem areas:
Mask and Resolution Enhancement Technology (RET) infrastructure.
Materials, photoresist and underlayers.
Metrology
The exposure tools are also of course key, but that isn’t what Steve talks to. Authors note – I will be doing a write up on ASML’s SPIE presentations as well.
Masks
Steve went on to list out mask related issues:
Mask 3d effects, such as focus shift and contrast loss – High NA is a low angle exposure making 3D effects more of an issue.
Low defectivity mask blanks and masks with low variability in roughness and CD
Low-n masks are needed to enable higher contrast and reduce mask 3D effects.
Optical Proximity Correction techniques.
Mask writing, multibeam.
Mask stitching – the smaller size of the scanner field requires that die be stitched together.
4x one direction, 8x other direction requires a new type of mask design to enable stitching.
Pellicles for higher source energy.
In “CNT pellicles: Recent optimization and exposure results,” Joost Bekaert et.al., explored Carbon Nanotube pellicles (CNT).
ASML has 600-watt source systems on their roadmap, current pellicles based on metal silicide are only viable up to approximately 400 watts. Pellicles need to block particles, have high transmission, sufficient mechanical strength to be suspended over an approximately 110mm by 140mm area, and be durable. CNT has showed up to 98% transmission. EUV radiation is so energetic that it creates a hydrogen plasma that etches the pellicle eventually leading to pellicle loss of mechanical integrity. imec has been evaluating etch rates and how to stabilize the pellicle.
Etch rates can be evaluated by looking at transmission, as the Pellicle is thinned by etching, transmission increases. Figure 1 illustrates the transmission over time of a Pellicle subject to various conditions.
Figure 1. Pellicle transmission versus exposure time.
ASML evaluates pellicle transmission versus exposure time utilizing an offline plasma exposure tool and in this work, imec demonstrated CNT pellicle exposure up to 3,000 wafers (96 dies at 30 mJ/cm² per wafer), and showed correlation between the results obtained from actual scanner exposure and those from the offline tool.
Pellicles initially have volatile organic impurities from the manufacturing process that absorb EUV energy until they burn off, see the green and purple curves. Baking the Pellicle at high temperatures “purifies” the pellicle by burning off the contaminants resulting in etch rate dominated transmission changes. The slope of the two blue curves is due to the etch rate. The green curve illustrates a “coated” pellicle that exhibits a lower etch rate, however the coating reduces transmission and may not be compatible with very high-power levels.
Photoresist
Steve, then discussed photoresist.
For photoresist a 24nm to 20nm pitch is a sweet spot for High NA insertion with 16nm pitch the ultimate resolution. Chemically Amplified Resist (CAR) has poor performance below 24nm. Metal Oxide Resists (MOR) look promising down to 17nm or even 16nm. Defectivity is still an issue. Doses at for a 24nm pitch is 67mJ/cm2 for MOR and 77mJ/cm2 for CAR. MOR has some stability issues and the lower the dose the more reactive/less stable the resist is. These are challenges, not showstoppers.
In “Scaled down deposited underlayers for EUV lithography,” Gupta et.al., explored photoresist underlayers. As pitch is shrunk, for the same photoresist layer the aspect ratio increases and can lead to pattern collapse. Improved underlayer adhesion can address this. Alternately a thinner photoresist can be utilized to manage aspect ratio but this can lead to etch issues unless a high etch selectivity under layer can be found.
imec found that surface energy of deposited underlayers can be matched to the photoresist to achieve improved adhesions. Density tuning of the deposited underlayer can be utilized to provide improved etch selectivity.
In “Dry Resist Patterning Readiness Towards High NA EUV Lithography,” Hyo Sean Suh et.al., from imec and Lam explored Lam’s dry photoresist process. For N2+ and A14 processes Metal 2 pitch (M2P) is expected to be ~24nm with 15nm tip-to-tip (T2T) and then at A10 M2P will be ~22nm with <15nm T2T.
The Lam dry resist process is illustrated in figure 2.
Figure 2. Lam Dry Photoresist Process
Post Exposure Bake (PEB) was found to strongly drive dose reduction but affected bridges and roughness. Co-optimizing development and etch mitigates bridges and roughness and showed a robust process window for 24nm pitch L/S patterning.
In “Feasibility of logic metal scaling with 0.55NA EUV single patterning,” Dongbo Xu et.al. described an evaluation of what High-NA (0.55NA) system can achieve with single patterning.
They concluded that 24nm pitch looks achievable. 20nm looks promising in the horizontal direction but the vertical direction needs more work. 18nm pitch needs additional work.
EUV has proven to be a very challenging technology from a Line roughness and stochastic defect perspective. Directed Self Assembly (DSA) is a technology that has been around for a long time but hasn’t gotten much traction. DSA is now getting attention as a technique to address line roughness and stochastic defects for EUV.
In “EUV LITHOGRAPHY LINE SPACE PATTERN RECTIFICATION USING BLOCK COPOLYMER DIRECTED SELF ASSEMBLY: A roughness and defectivity study,” Julie Van Bel et.al. found that combining DSA with EUV is superior to DSA processes based on Immersion lithography with lower line width roughness and no dislocation defects.
In “Mitigating Stochastics in EUV Lithography by Directed Self-Assembly,” Lander Verstraete et.al. explored using DSA to mitigate stochastic defects in EUV processing.
The imec process to rectify line/space EUV defects is illustrated in figure 3.
Figure 3. EUV Line/Space Pattern Rectification by DSA.
The imec process to rectify defects in contact arrays is illustrated in figure 4.
Figure 4. EUV Contact Pattern Rectification by DSA.
EUV plus DSA looks very promising for line/spaces at a 28nm pitch with the primary defect being bridges. At a 24nm pitch improvement is needed with too many bridge defects. Defects correlate with the block copolymer formulation and anneal time.
For contact arrays EUV + DSA improves Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error and enables a lower dose.
Metrology
As film thicknesses are reduced metrology signal to noise ratios become a problem.
With EUV there is a defectivity process window, on one side there is a cliff where breaks in the pattern become an issue and on the other side of the windows there is a cliff where bridges between patterns become a problem.
When a new pitch is attempted there are a lot of defects that are driven down over time.
It is hard to measure a large enough area with sufficient sensitivity. E beam inspection is sensitive but slow, optical is fast but not sensitive. New 3D processes like CFET introduces additional challenges.
In “Dry Resist Metrology Readiness for High NA EUVL,” Gian Francesco Lorusso et.al, investigate Atomic Force Microscope (AFM), E Beam inspection and CD SEM for characterization of very thin photoresists.
Using the Lam dry photoresist process< CD SEM was shown to be viable down to 5nm thick photoresist. As resist thickness decreased line roughness increased, printability of bridge defects decreased while break defects remained the same. Pattern collapse was only seen in thicker films. AFM measurements indicated film thickness decreases. E Beam showed good capture of defects even for very thing films.
In “Semiconductor metrology for the 3D era,” J. Bogdanowicz et.al., explore the challenges of metrology on 3D structures.
In the 3D era, the Z direction has become the new X/Y scaling. For logic devices, CFET and Semi damascene presents challenges, in memory 3D DRAM is a future challenge, and 3D interconnects for System Technology Co Optimization (STCO) are another challenge.
For Horizontal Nanosheet and CFET processes lateral recess and fill characterization and detecting residues and other defects in multilayer stacks will be critical. In 3D Memory high aspect ratio (HAR) hole/split profiling and similar to logic detecting buried defects and residues in multi layers films will be critical. For STCO applications integrity of bonding interfaces and alignment will be key.
For traditional surface metrology there is already a trade off between sensitivity and speed, now inspection depth versus lateral resolution is a key trade off. Figure 5 presents the probing depth versus lateral resolution and throughput for various metrology techniques.
Figure 5. 3D Metrology Landscape
Figure 6 summarizes the current readiness of 3D metrology to address various needs.
Figure 6. 3D Metrology Challenges
From figure 6 there are still a lot of challenges to overcome to achieve a comprehensive metrology program.
Conclusion
The era of High NA EUV is approaching. There is good progress being made in pellicles, photoresists, and metrology and imec continues to work in all three areas for further progress.
The headline is: Ansys Signs Definitive Agreement to Acquire Diakopto, Expands Multiphysics Simulation Portfolio for Semiconductor Designers. The acquisition complements Ansys’ existing signoff solutions and enables integrated circuit (IC) designers to detect problems earlier in the design flow.
Which is certainly true but let me tell you what Diakopto really is, they are a diamond in the rough. A very large diamond. This is definitely one of those 1+1=3 types of situations, absolutely. Congratulations to John Lee and his Ansys M&A team on another amazing acquisition.
We have been working with Diakopto for less than a year but we have learned a lot about them. Starting with the CEO interview (Dr. Maxim Ershov) followed by a series of articles written by Maxim directly that earned an amazing amount of traffic.
Even though Diakopto was relatively young the customer list is most impressive with more than 30 companies using the tool. The only thing holding Diakopto back, in my opinion, was the sales and support channel which is no longer an issue with Ansys. Ansys has one of the strongest channels in EDA which is one reason why I enjoy working closely with them. Ansys and Diakopto also have very strong product synergy, which is highlighted below, thus the 1+1=3 reference.
Key Highlights
The addition of Diakopto’s solutions to Ansys’ portfolio will deliver a competitive edge to engineers using Ansys to create high-performance integrated circuits
Diakopto’s unique and market-leading products complement Ansys’ existing solutions – the combination will empower our customers to deliver optimal designs and accelerate time to market
The transaction is subject to the satisfaction of customary closing conditions and is expected to close in the second quarter of 2023
PITTSBURGH, May 16, 2023 /PRNewswire/ — Ansys, (NASDAQ: ANSS) the global leader and innovator of engineering simulation software, announced today that it has entered into a definitive agreement to acquire Diakopto. A provider of differentiated EDA solutions to accelerate integrated circuit (IC) development, Diakopto focuses on helping resolve critical issues caused by layout parasitics. The transaction is subject to the satisfaction of customary closing conditions and is expected to close in the second quarter of 2023. It is not expected to have a material impact on Ansys’ consolidated financial statements in 2023.
Ansys has entered into a definitive agreement to acquire Diakopto
Diakopto develops products that address the growing complexities and unintended effects of designing ICs in the modern era. Semiconductor designs increasingly employ advanced process node technologies, where interconnect parasitic effects limit the performance, reliability, and functionality of designs. Diakopto’s market-leading products have been adopted by dozens of customers, including tier-one semiconductor companies, for a broad range of applications.
With the acquisition, Ansys will better enable design engineers to “shift left,” and to detect interconnect parasitic problems early in the design cycle. Diakopto’s products provide actionable analytics to guide designers to fix these problems – a capability that has not existed before. Through early identification and what-if analysis of parasitic problems, engineers can minimize costly iterations late in the design cycle – furthering cost and time savings.
“Diakopto’s culture of strong engineering excellence and its innovative and highly differentiated products create a natural alignment with our organization. We are eager to welcome their team to the Ansys family,” said Shane Emswiler, senior vice president of products at Ansys. “Incorporating Diakopto’s unique methodology will support designers using Ansys to quickly and easily pinpoint the few elements, out of billions, causing bottlenecks. Designers can then optimize and debug designs more efficiently for enhanced IC performance and reliability, and accelerate time to market. The acquisition will complement Ansys’ existing offerings for engineers at every level as Diakopto’s intuitive and out-of-the-box experience doesn’t require extensive training or complicated setups or configurations.”
“Today’s announcement brings together two like-minded companies on the forefront of innovation, and we are excited about becoming part of the Ansys family,” said Maxim Ershov, CEO and CTO at Diakopto. “By joining forces with Ansys, we’re confident that we can solve a broader set of problems in the chip design workflow together, strengthening offerings for our customers and driving more innovations in high-tech designs for data center, 5G, automotive, and mobile applications.”
About Ansys
When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys.
Take a leap of certainty … with Ansys.
Ansys and any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries. Diakopto and ParagonX are trademarks of Diakopto Inc. All other brand, product, service and feature names or trademarks are the property of their respective owners.
Contacts
Media
Mary Kate Joyce
724.820.4368
marykate.joyce@ansys.com
As we all know design starts are the life blood of the semiconductor industry, both big and small. Enabling those design starts is what the semiconductor ecosystem is all about and Efabless has a very unique value proposition in this regard.
Efabless is a free cloud-based chip design platform, growing community of 9000+ chip designers, and fabrication friendly technology company that takes you from idea to silicon inside your product. Only Efabless chipIgnite provides a complete end-to-end solution for creating your own chip at a very low cost. Established in 2014, Efabless has a thriving community of thousands of chip designers putting more than 400 chips to fabrication.
I’m friends with the Efabless CEO and CTO and I have followed this journey since the beginning. As I well know building an online semiconductor design community is a very difficult thing. It is an underappreciated never ending job. Efabless however has done something very clever here and I see continued growth opportunities ahead, absolutely.
Show the World how Innovation can Move from Prompt to Silicon in Record Time!
Generative AI offers the potential to accelerate chip innovation by putting chip design into the hands of more people than ever before and enabling them to design faster and for less cost.
In this Challenge, we aim to show how a community can use this powerful new tool to deliver interesting designs in a matter of weeks.
Award:
Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless.
Requirements:
All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation. Stay tuned for more details!
Judging Criteria:
– Project Documentation
– Prompt Documentation
– Code
– Verification Coverage
– Technical Merit
– Community Application Interest Poll
– All requirements must be met to be eligible to win
– All submission content, documentation, prompt must be in English
– A short description of the project must be included with your design. It will be used for introducing your idea in the community poll.
– All designs must be implemented and fit in the Caravel User Project area.
– The Verilog for the design must be coded by AI.
– Verification may be done outside of the AI environment but verification testbenches must be provided as a reproducible element of this process.
– All prompts or auto GPT session logs used in the design must be provided as part of the deliverables for the design.
The design needs to be open source with all materials required to reproduce made public.
The design must be implemented using the OpenLane chipIgnite flow including all configuration and run results.
Must have testbenches for RTL verification as well as constraints for STA and SDF simulations.
Must be implementable in SKY103 with available standard cells and DFFRAM and not require open RAM or other discrete memories for implementation.
The design must pass precheck and tapeout submissions on the eFabless platform.
Winners will be expected to provide a video and screenshots demonstrating the creation of the project in a how-to or step-by-step format. These materials may be used by eFabless for promotional purposes.
Official Rules
-Eligibility
Participants must be able to receive silicon and parts shipped from the United States. As such, members of United States embargoed or sanctioned countries are not eligible to participate. Current employees of Efabless or their family members are also not eligible to participate.
-Deadline
The submission deadline is Friday, June 2, 2023 at 11:59 pm PT.
-Sponsorship
The contest is sponsored by Efabless Corporation, 165 University Ave, Palo Alto, CA 94301
-Agreement to Official Rules
Participation in the contest constitutes participant’s full and unconditional agreement to and acceptance of these Official Rules and the decision of the Sponsor, which are final and binding.
An entry may be rejected at the sole and absolute discretion of Efabless.
By entering the contest, you agree and allow Efabless to use, display, and publish a winner’s identity, including their name and photo, in promotional materials. The participants also agree that Efabless has the right to use participant’s designs and other material in sales and marketing.
How to Enter
Register on the Efabless platform if you have not already done so.
Submit your entry by including all content on a public GitHub repo.
Create a public project for the chipIgnite 2306Q shuttle using the GitHub repo from the previous step.
Submit success precheck and tapeout jobs for your design.
Complete the remainder of the billing and shipping information as well as terms and export agreements. You will not be charged or invoiced for your submission. Complete the final submission for the project on the platform.
Send an email to shuttle@efabless.com with a link to your project.
Limit one entry per person, per email address. Your entry must be original.
Note: If you have not received permission to use copyrighted material, you may not include the material in your entry.
Contest Winner Announcement
Contest winners will be announced on Friday, June 9 2023. The winner will be provided fabrication at no cost in the June 5th chipIgnite shuttle, 2306Q.
It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor industry, what is driving that trend, and what EDA’s role is to support and drive this growth. Joe finished his keynote by identifying the thrust of Siemens EDA’s R&D efforts and providing a couple of examples.
Here is a high level synthesis of Joe’s keynote presentation.
Historically speaking, the semiconductor market has been a cyclical market with the memory market segment having an oversized influence on the overall market growth. Cyclical trends are affected by the boom and bust swings of the market. A secular trend on the other hand is one that is likely to continue moving in the same general direction for the foreseeable future.
Drivers Behind the Secular Trend
The worldwide aggregate data traffic growth rate is 2x per year with the data being created, transmitted, processed and stored by semiconductor devices. Semiconductors are taking a more important role than ever. This is reflected by statistics that show how the semiconductor content share of system product value has grown over the last few decades. From an average of 8.3% until the late 1980s to 16% until mid 2010s, it has reached 25% now and projected to go up. More and more intelligence is being built into systems. Systems companies have noticed this and getting directly involved in System-on-Chip (SoC) designs and tapping pure-play foundries. This is to ensure optimization of profitability of their systems and for the differentiated use of intelligence-driving technology into their products. The above are the drivers behind the secular growth trend for semiconductors. The number of design starts are projected to continue to grow at 5% driven by many new growth applications. Market Research firm IBS is predicting that artificial intelligence (AI)-driven semiconductors are going to be the major market driver behind the growth to the trillion dollar mark.
Three Pillars of Siemens EDA R&D Investment
Siemens EDA is focusing on three pillars of R&D investment to support the secular growth trend.
Design scaling – extracting more functionality and performance from the designs themselves on top of what the doubling of transistors every two years.
System scaling – system complexity is growing at a much faster rate than 2x. Understanding how a system will respond over time which in turn requires an understanding of how the ICs will respond over time. Looking at new ways of system level verification to help build better designs to solve the end customers’ needs. For example, autonomous vehicle systems or other IoT based systems.
An area that cuts across all three pillars is the system technology co-optimization (STCO) for 2.5D and 3D ICs. Multiple Dies into one package in an optimal way to meet the cost, power, thermal and performance goals is not an insignificant challenge.
How Does Siemens EDA Support the Secular Growth Trend
At Joe’s keynote was time-compressed to accommodate time for two more keynote talks, I followed up to gain additional context and insights for this post.
For a 10 year (2020-2030) CAGR for semiconductors, Market Research firm IBS [Report: May 2022] is projecting a 32.4% for semiconductors with AI content compared to a meagre 3.3% CAGR without. While the AI hardware will be the critical driver for applications and semiconductor volume, off-the-shelf IP will be insufficient to address power and performance. The ability to create unique AI silicon content rapidly is challenging but also a critical success factor for the next generation of applications. That is why, design scaling and system scaling are taking on even more importance going forward.
In the design scaling category, the areas of focus include creation of high-quality RTL, advanced digital implementation for out-of-the-box PPA, data-driven verification and end-to-end test solutions.
As an example, High-Level synthesis through GDSII (Siemens EDA Catapult) enables accelerated creation of unique AI IP. The premise is that moving the design to even higher level than RTL, say to C-level approach enables much more architectural exploration to be achieved. For example, analyzing the effects of varying bit widths, memory structures, etc. Integrating the results from these analysis into a detailed place and route environment makes it possible for very good prediction of overall performance.
As for system scaling category, execution of system software on the SoC is critical. And so are the integration and validation within the system context to ensure the correct operation of complex systems. The scope of what Siemens EDA brings to its customers to support their system scaling requirements is immense.
Following is an automotive system example that Joe shared during his talk. It takes sensing and traffic data, connects to a decision framework and then to an actuator braking system. The breadth and depth of the processing and Multiphysics analysis to be performed to simulate an accident scenario in a metaverse city environment is tremendous. Siemens EDA customers are able to get these capabilities under one roof. Siemens PAVE360 is one such demonstration. PAVE360 is a complete autonomous verification and validation environment modeled as a system that represents a twin image of the physical vehicle and its driving surroundings. Siemens PAVE360 powers the needs of OEMs and suppliers to explore, design, build and train/validate compute solutions critical to the future of connected and autonomous driving cars.
Summary
The semiconductor industry has become a central point in the awareness of most governments around the world with the tail wind likely to further strengthen the secular trend presented by Joe. During the User2User conference, many customers provided substantiation of how Siemens EDA’s various tools and solutions are addressing their market requirements and the secular growth trends. SemiWiki will be posting separate blogs on many of these presentations.
During the recent COVID pandemic it was common to read about automobile companies unable to deliver new vehicles, caused by the shortage of specific automotive chips. Even bad weather has shut down the supply of semiconductor parts to certain customers. This disruption of the IC supply chain has caused many companies that buy and use semiconductors to consider moving some of their chip designs to in-house programs. A recent white paper from Methodics addressed the challenges of in-house chip design.
Success stories of systems companies doing their own chip designs include Apple, Tesla, NVIDIA, Qualcomm and Broadcom. Designing ICs along with their embedded software requires experience and best practices. Many components of ICs are building blocks called IP, and there’s a whole ecosystem to choose from pre-built, common functions, like: Radios (Bluetooth, WiFi), RAM, ROM, Processors, USB, etc.
Semiconductor design also has risks and high costs from both the EDA software for design and photomasks involved in fabrication. Calculating the ROI at the very start of an IC project is required, and using an IP-based approach is a best practice. Modeling your new IC as IP blocks allows your engineering group to compare in-house development versus purchasing IP from a third party. Planing and tracking all IP is foundational to model costs and track development progress.
The Methodics recommended methodology is to start with a planning Bill of Material (BoM) to evaluate tradeoffs and perform analysis. Using a general-purpose Product Lifecycle Management (PLM) tool for 3rd party semiconductor components, and a semiconductor planning BoM tool for the in-house chip design, enables you to compare each approach. The combination of PLM and Methodics IP Lifecycle Management (IPLM) tools is shown below, as part of the build or buy decision process to improve your supply chain.
Perforce Methodics IPLM Planning BoM
The Planning BoM has all of the details for each hierarchical IP being used, along with version history as each IP goes through a release cycle. Your team transitions from using the Planning BoM to an execution BoM while using the Perforce IPLM.
Execution BoM
The IP hierarchy is defined in the Execution BoM and it should support popular data management tools like Git or Perforce Helix Core. Any version conflicts need to be automatically identified in both hardware and software IPs to keep compatibility.
Multiple DMs
Both hardware and software IPs are managed in this approach, making sure that requirements can be traced for every component. You will know which software component is delivered for each hardware component, ensuring transparency.
Release engineers are tasked with tracking each release candidate and managing the integration process, and using Methodics IPLM automates the manual integration and curation processes.
Meta-data can be used during the design process to account for ISO 26262 functional safety compliance requirements per IP. Traceability of requirements to IP blocks is captured with Methodics IPLM. Even security meta-data can be added on the IP or component hierarchy to help asses the security threats for each project, as you reference an internal IP Security Assurance (IPSA) catalog of issues for a circuit.
Summary
Systems companies are gradually adopting in-house IC design projects as a means to reduce supply chain bottlenecks. Using an IP-centric methodology is a best practice to control your ROI and start building IP re-use. The Methodics IPLM platform has been around for many years, helping to manage the challenges of IP-based design across entire corporations.
Benefits of this approach are: traceability of requirements, managing IP re-use, having a centralized catalog of all IP – hardware and software, having both planning and platform BoMs, and having analytics to see where you are at.
Chiplet is a hot topic in the semiconductor world these days. So much so that if one hasn’t heard that term, the person must be living on a very isolated islet. Humor aside, products built using chiplets-based methodology have been in existence for at least some years now. Companies such as Intel, AMD, Apple and others have integrated in-house chiplets to build these products. But the bigger opportunity lies in being able to build products using heterogeneous chiplets, meaning chiplets from multiple vendors. Heterogeneous chiplets integration poses many technical and business challenges to overcome.
The Open Compute Project Foundation has a subgroup called Chiplet Design Exchange (CDX) that is now focused on tackling the technical challenges. The effort is a collaborative one with Palo Alto Electron, Siemens EDA and many other companies and individuals participating and contributing. Jawad Nasrullah, CEO of Palo Alto Electron gave a talk at Siemens EDA’s User2User conference in Santa Clara, CA. The following are excerpts from that presentation.
Design management of chiplet projects can be broadly divided into four stages, namely architecture, design execution, verification and signoff.
The architecture stage needs to consider multiphysics including thermal, warpage, structure, etc., on top of the conventional power, performance and area (PPA) metrics. The goal is to generate a top level golden netlist based on all of the above considerations. Even a simple design could have tens of thousands of nets and typical designs could have nets in the millions. The Open Compute Project/ODSA subgroup is happy with the capabilities of Siemens EDA’s XSI tool for managing the golden netlist.
Design automation and management become very critical in a multi-vendor tools environment. In dealing with substrates for chiplets-based designs, bridges, interposers, etc. make things more complicated. A standardized workflow is needed to tackle the many challenges. Siemens EDA’s XPD solution does a pretty good job although there is room for improvement. Current tools in the market fall short a bit as they are being repurposed from their PCB oriented purpose to support packaging for chiplet-based designs. Participants and contributors to the CDX subgroup project are using Siemens Calibre 3D for signoff related R&D, making it easier to use the Siemens XSI generated golden netlist.
The above is the foundation for the work being done in CDX, with the goal of design automation standardization. In order for EDA tools from multiple vendors to be able to exchange design information, models need to be standardized and described in machine readable format.
The goal of CDXML is to provide a standardized format for describing chiplets, which will enable chiplets from different vendors to be easily integrated into a single system-on-chip (SoC) design. CDXML is designed to be compatible with existing Electronic Design Automation (EDA) tools and workflows, which are used to create and verify chiplet-based designs. Once the chiplets are defined, they need to be modeled to capture their thermal, physical, mechanical, I/O, behavioral, power dissipation, signal integrity, power integrity and testability aspects. A chiplet design kit (CDK) is a collection of tools, models and documentation that enable designers to create and verify complex chiplets-based SoCs. CDKs are to be provided by chiplet vendors in a heterogeneous chiplets market place.
CDX subgroup participants including Palo Alto Electron and Siemens EDA have contributed to a proposed standardization effort for chiplets modeling for heterogeneous integration.
You can download the whitepaper here. Those involved in chiplets-based designs currently or will be in the future will find this whitepaper very useful.
Dan is joined by Paul Wells, CEO of sureCore. Paul has worked in the semiconductor industry for over 25 years. His experience includes Director of Engineering for Pace Networks where he led a product development team creating broadcast quality video & data silicon. He worked for Jennic Ltd as VP of Operations successfully building the team from scratch as the company transitioned to a fabless model. Prior to that, he was responsible for the engineering team. Paul also led a team for Fujitsu Microelectronics supporting ASIC customers in Europe and Israel.
Dan explores the inner workings of sureCore’s new PowerMiser memory IP with Paul. Paul explains how sureCore can achieve ultra-low power and small footprint memory architectures. He explains the importance of customer collaboration to achieve these results and discusses critical applications both today and tomorrow.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Every country realizes the importance of producing skilled chip designers who could decide their success as soldiers by creating advanced AI chips for winning the Chip War. Also, every country is now gearing up to build a good semiconductor manufacturing ecosystem to balance the global semiconductor supply chain that could overcome any more supply chain disruptions experienced during the pandemic. But the advanced foundries without next-gen chip designers would be the same as ‘Fabs without Chips’. So, in this article, I want to inspire the electrical and electronics engineers who can lead the semiconductor industry as the next generation of chip designers, sharing my insights and explaining how ‘Semiconductor rules the world’. Also, I hope this article inspires the VLSI Design companies to upskill and support their chip design workforce for their long-term VLSI career development, prioritizing and investing in their Learning and Development initiatives.
1.Chip War
The geopolitical AI cold war between the US and China is perceived as Chip War. Artificial Intelligence technology is one of the essential technologies for any country to emerge as the most powerful country with its next generation of defense and space technologies. Chip war is all about fighting for their dominance in AI.
The AI systems can be trained on vast data centers built with cutting-edge AI chips. So, every country is funding and collaborating with global chip manufacturing companies to build advanced fabs for their future.
The advancement and implementation of AI technology rely on semiconductors, and it demands semiconductor architectural improvements. The improvements in chip design for AI will be less about improving overall performance and more about speeding the movement of data in and out of memory with increased power and more efficient memory systems.
Only with higher technology nodes we can fabricate complex SoCs as cutting-edge AI chips that integrate complex neural engines and memories using new technologies like Chiplets. So, every country is gearing up with advanced fabs.
2.Chip Industry
Our journey in the semiconductor industry started with making IC with four transistors, and it’s continuing to produce complex SoCs with 100s of billions of transistors.
2.1 History:
Defense has been a key driver for the evolution of the semiconductor industry. Defense departments & institutes, especially DARPA in the US, funded inventing chip technologies and introduced the concept of using chips to create advanced defense technologies like next-gen missile guiding systems.
The first monolithic IC was invented by Robert Noyce at Fairchild Semiconductor. In 1960 first operational IC was created at Fairchild. Later the chip manufacturing ecosystem was built with a supply chain[Machines and materials] spread across Taiwan, Netherlands, South Korea, Japan, and other countries, beyond the US. The chip industry emerged from Texas, Silicon Valley, and expanded into other countries like Taiwan, as a global industry. Today more than 90% of the advanced chips are manufactured in Taiwan, mainly by top foundries like TSMC. Chris Miller’s book ‘Chip War’ can walk you through the incredible journey and evolution of the chip industry.
2.2 Semiconductor Ecosystem:
The global semiconductor industry is generating yearly revenue of 500+ billion USDs and growing exponentially towards generating 1 trillion USD by 2030. In my view, it reflects the evolution of VLSI technology. In terms of technology, we are making SoCs with 100+ billion transistors and evolving towards making chips with 1 trillion transistors by 2030.
2.3 Inventions and Innovations:
The semiconductor ecosystem incorporates various players like OEMs, IDMs, Fabless-IP, EDA, and Foundries. The ecosystem is evolving with all the inventions and innovations by its players/stakeholders. Every stakeholder contributes equally to the growth of the global semiconductor industry, and some of the highlights I am listing here for your reference.
OEM: Apple is adopting a smartphone-design approach for their MacBooks. Its M-series SoCs are now built with ARM RISC processors using 5 nm technology, replacing the popular desktop CISC processor, and the complexity ranges from 16 billion to 100 billion transistors.
IDM: Intel is growing its foundry business with the vision of creating an open system foundry to empower the chipmakers to create a System of Chips[SoC] using various technologies like 2.5D&3D advanced packaging, Chiplets with Universal Chiplet Interface UCIe, and System Software solutions.
Fabless-IP/Chip: ARM is still ruling the semiconductor industry as the most successful IP company, with the credit of having hundreds of billions of electronic devices shipped with ARM cores. World’s fastest supercomputer Fugaku built with more than 7 million ARM cores, is one of the highlights beyond its dominance in the smartphones, IoT, and Automotive market segments.
RISC-V open ISA began its journey of open era of computing from the CPU graveyard, where we witnessed the burial of many proprietary specialized ISAs. Now RISC-V is emerging as an industry standard open ISA for all kinds of processors, general purpose and specialized processors. Esperanto, SiFive, Western Digital, Alibaba, and many more have been creating new powerful processors and cutting-edge AI Chips with RISC-V open ISA and empowering the semiconductor ecosystem.
Nvidia and AMD continue to rule the global semiconductor industry as fabless chipmakers with their next-gen state-of-the-art GPUs and CPUs.
EDA: EDA is acquiring intelligence using AI technologies to help designers achieve optimal PPA results. Synopsys has recently released Synopsys.ai as the first full-stack AI-driven EDA suite for chipmakers, following its successful DSO.ai for Design Space Optimization. EDA on the cloud similar to SaaS and Multi-die-system solutions are some of the other innovative EDA solutions from the EDA industry.
Foundry: Intel is expanding its foundry business with its open system foundry vision for advanced fabrication. TSMC is also expanding its foundry business in the US beyond Taiwan. Other players like Samsung and Micron are also investing heavily in building new foundries with advanced fabrication technology. Following the US Chips Act funding, every other country well known for semiconductor design, including India, is investing heavily in this fabrication space towards becoming self-reliant.
2.4 Investments:
The US introduced Chips ACT funding with USD 280 billion to boost semiconductor R&D and manufacturing in the USA. Currently, the US is producing only 10% of the chips made globally and aims to achieve 30% by 2030.
India introduced USD 10 billion incentive package for building a semiconductor chip manufacturing ecosystem in India. Foxconn and Vedanta seek to bring European chipmaker ST Microelectronics as their technology partner in their proposed India manufacturing unit. ISMC (US$3 billion investment) and Singapore-based IGSS (investment worth INR 256 billion) will set up semiconductor plants in Karnataka and Tamil Nadu, respectively.
2.5 Opportunities:
As per the Deloitte report, 2 million direct employees run the global Semiconductor Industry, and this fast-growing industry needs additional 1 million workers by 2030.
India has a very fast-growing electronics system design manufacturing (ESDM) industry. According to the Department of Electronics and Information Technology, nearly 2,000 chips are being designed annually in India. More than 20,000 VLSI engineers are working on various chip design and verification aspects.
Semiconductor Fab units require huge investments, gallons of water for production, uninterrupted electricity supply, high operating costs, and frequent technology replacement. This is why India’s contribution to the global semiconductor industry has focused on its technical competencies in R&D, design, etc., due to its talent pool in IT design and R&D engineers.
Academia with 2500+ engineering colleges produces 1.5 million engineers in India. Only 2.5 lakh engineers succeed in getting jobs in the IT sector. Excluding the IT software services, only 50000 engineers enter into the core industry, including all the domains. The number of engineers directly enter into the Indian Semiconductor Industry could be in the range of 5000 to 10000, which is insufficient. So, we at Maven Silicon bridge the gap between academia and the semiconductor industry, collaborating with our industry partners and academia in India. Also, Maven Silicon emerged as a VLSI Centre of Excellence[VLSI-COE] for the global semiconductor industry, upskilling the workforce[experienced VLSI engineers] worldwide using our corporate VLSI training solutions.
3.Summary
Software giants Amazon, Microsoft, Google, and Facebook are now building their chip design centers and making their chips for their data centers. The emerging technologies AI, 5G, Cloud, IoT, and Automotive demand more advanced chips and accelerate the semiconductor industry’s growth further. So the global semiconductor industry needs millions of skilled VLSI engineers to meet this growing demand and emerge as a trillion-dollar industry by 2030.
It’s very evident from history that the semiconductor industry rules the world beyond wars. Robert Noyce, Jack Kilby, Gordon Moore, Morris Chang, and many more great engineers and entrepreneurs ruled this semiconductor industry with their inventions and innovations and built the semiconductor ecosystem as architects. As a curious electrical engineer reading this article, you could be the next one continuing this incredible journey as our hope.
