A User View of Efabless Platform: Interview with Matt Venn

A few months ago, SemiWiki published an interview of Mike Wishart, CEO of Efabless. That interview provided insights into Efabless vision and its platform strategy. If you haven’t already read that post, please refer to it for background details. In essence, Efabless is about democratization of chip design and manufacturing. Whether you are a professional, company, academic, or hobbyist – the Efabless platform is a fast, simple, inexpensive way to produce your custom chips. Just as YouTube enables everyone to become a creator of published video content, Efabless helps software and hardware developers create their customized chips.

The following interview with Matthew Venn is to bring out a user’s perspective of the Efabless platform. Matt is a science & technology communicator and electronic engineer.  Matt has used the Efabless platform to create multiple designs and has submitted designs on all 4 open MPW runs to date.  After applying to MPW1 he created a course that aims to teach you everything you need to know to go from zero to ASIC. You can find out more about him and his course at ZeroToASICcourse.com.

Also, feel free to connect with Matt on LinkedIn: https://www.linkedin.com/in/matt-venn/ or Twitter: https://twitter.com/matthewvenn

What is your motivation behind the chip projects you are working on?

It started off purely as personal interest. I saw Tim Edwards from Efabless presenting a chip he had designed using QFlow, an open-source ASIC flow. I was working on an FPGA project at that time, so I tried a couple of small designs just to see how QFlow worked.  It was really eye opening to see the different parts of the ASIC flow. I posted some screenshots on Twitter and lots of people were interested. I started looking into running some kind of training that would result in people getting chips in hand. At the time, this meant finding 10 people who’d be willing to pay a few thousand dollars each for a course.

A few months later we had the announcement from Tim Ansell about the Google sponsored free shuttle in collaboration with Efabless and Skywater. I watched the FOSSi dial-up talks and tried the OpenLane flow when it became available. It looked like I’d be able to put my design onto some real chips – a really exciting moment!

The interest I saw from my peers led me to create the Zero to ASIC course, and that has gone on to train 130 people around the world. We’ve applied to all of the MPW runs, with about 30 people from my course submitting designs to the tapeouts.

To summarize, my motivation is about learning and teaching, being involved in this exciting moment of open-source chip design, and taking advantage of getting free chips!

What caused you to look at an open-source approach for your projects?

I’ve worked independently for so long, so a big part of the appeal of open-source to me is the community. I can learn and share, write docs, create videos and be part of a movement without needing to physically be in a company that is using those specific tools.

Of course, the Efabless Open MPW shuttles sponsored by Google are only available if the designs are open-source, so for getting chips made for free, open sourcing my designs was essential.

How did you learn of the Efabless platform and what pushed you to try this platform?

I heard about it through the FOSSi dialup YouTube series. It was the opportunity to get some of my designs in silicon that pushed me to get involved. If I had known how hard it was going to be at the beginning, I might not have done it! You know that saying – sometimes you have to not know the journey in order to embark on it. And that’s also fed into me creating my course. I wanted to have a journey from end to end that would take someone from zero to ASIC.

What was your first project using the Efabless platform? How would you describe your experience? How many projects have you done so far?

My first project was on the first shuttle, the Open MPW-1. I had a couple of open-source FPGA designs already and I thought I’d try them out. This was when I realized how large a space the Efabless Caravel harness provides (or how small my designs were!). So, I asked a few friends if they’d like to get involved and that was how I came  up with the idea of what I call a “multi-project-multi-project-wafer” or MPMPW! In the first run, we used a MUX to allow all the designs to have access to all the pins.

One of the cool things that Efabless have done is to create the Caravel harness – which includes a lot of basic building blocks that we can reuse to save time. A key part of it is a RISC V CPU that can configure the GPIOs, and we can also use it to select which design is active.

By the time of the second shuttle, the Open MPW-2 – I had created my course and 14 participants made designs to put on the MPMPW.  One thing that’s really attractive about the new ecosystem is how practical the course can be. It’s unusual to have the tools locally installed and to also be able to take part in a real tapeout.

In MPW-3 we managed to place a 1kB SRAM generated by the OpenRAM memory compiler along with 7 other designs from the course.

For MPW-4, we made that memory available via wishbone to the other designs on the MPMPW, and included 10 designs from people on the course. Two designs made use of the local fast memory, a CPU by Uri Shaked and a demonstration project by me.

What are the speed bumps and hurdles that you faced when trying to build your own chips?

As there is a lot new in this process – new tools, new PDK, a lot of people new to the field – there are a lot of problems that are being discovered and solved.  The first few shuttle runs, we had a lot of changes to the tooling at the last moment, even after the scheduled tapeout dates. Mostly, this was due to discovering critical issues that needed patches made to the tools, and participants needing to re-run their designs on the updated tools.  As a result, this has led to long feedback times.  By the time this article goes out, I’ll have submitted to 4 MPWs, but I am only now getting the first chips back to test. I could have made mistakes but not learnt about them till now.  The good news is that the issues are being solved. The better news is that this open model has allowed us to have visibility into the issues and help in the solutions.

I’ve learnt a lot over the last year – and there’s still more to learn. I like Feynman’s philosophy – if you want to learn, you should teach. It really exposes what I don’t know.  For example, I didn’t really fully understand what hold violations were, until recently.

Tell us about your multi project tooling that lets you aggregate more designs into an MPW submission. How cheap is it to build a chip through this platform?

When I discovered how small my designs were, I thought it was a shame to waste all the extra space. On MPW-1, I manually wired everything up, but it was pretty scary making changes. Since then, I’ve developed some open-source Python tooling that helps to join lots of smaller designs together. The tools can run a set of automatic tests and do some basic checks to make sure the designs are safe. All the outputs of the designs are tri-stated, and the firmware of the RISC V processor in the Efabless Caravel harness keeps them turned off until it’s their turn. This means that each design can use all 38 IOs.

At the moment we are applying to the free shuttles. Efabless also has a paid version of the shuttle called ChipIgnite, where your design doesn’t need to be open-source. So, if we combined 16 designs into one application, that would mean each applicant would pay just over $600 for 18 chips. Everything gets very affordable and fabrication gets accessible to a broader group.

You are an educator as well, teaching people to design and build their own chips. Tell us more.

By working in various startups over the years, I realized that when it comes to engineering, I’m much more of a generalist than a specialist. I’ve never focused on one area long enough to become a true expert. That used to bother me, but I’ve realized that it’s actually very valuable to have someone on the team that can help to bridge different areas, and especially to communicate difficult ideas to a broader audience.

I’ve always loved sharing what excites me about science and technology, which has led to a lot of science communication work. I think everyone knows the difference between really first-rate training and the truly awful boring kind. I’m always looking for ways to make my training accessible, entertaining, and practical.

I think one of the reasons there is so much interest from people about the open-source ASIC tooling is because this makes such a difference to the accessibility of training. Now I can have a VM with all the open-source tooling ready to go, and people can come on my course without having to do complicated setup or signing any NDAs.

Give us examples of exciting innovative chips that you’re developing through the Efabless platform.

You can see all the designs that went on MPW-2 , MPW-3 and MPW-4 here:

https://www.zerotoasiccourse.com/post/mpw2-submitted/

https://www.zerotoasiccourse.com/post/mpw3/

https://github.com/mattvenn/zero_to_asic_mpw4

It’s hard to choose the most exciting or innovative among them, but some interesting experimental work would be a PUF and EM glitch detector.

OpenPUF:

• Author: Pedro Rivera
• Github: https://github.com/pedrorivera/wrapped_OpenPUF
• Description: A delay-based physically-unclonable function (PUF) proof of concept

hoggephase

• Author: David Hulton
• Github: https://github.com/h1kari/wrapped_hoggephase_project
• Description: Hogge Phase EMFI/BBI Glitch Detector

What would you tell software engineers who would like to try their hand at building their own chips to run their software?

I’d say it depends on your interest. I’d break it into two recommendations for different people.

If you are coming to this out of an interest to know how chips are designed and made, then start off simple and build something very basic at a low level. For example, make a PWM driver in Verilog or VHDL.

If you want to build a custom SoC for a RISC V CPU, then use a framework like LiteX that magically automates a lot of the pain away.

What misconceptions or apprehensions did you have before you tried the open ASIC shuttle project first-hand?

It was one of those cases where I really didn’t know what I didn’t know. And I’ve still a lot to learn. You have to remember I only have 1 year of experience with ASICs!

What would you tell experienced hardware engineers who might hesitate to try their hand at using the open-source tools and the Efabless platform?

I would set expectations. Don’t expect the open-source tools to have parity with the proprietary ones in creating a fully optimized design for power, performance and area. In my opinion, that won’t happen for a long time, at least for more advanced technologies. That being said, the open-source tools plus functionality provided by Efabless knocks down the barriers that stopped most of us from getting to a real design.  For example, I think users will find the solution very effective for proof of concepts and it is a viable path for creating the custom silicon that you need for your hardware.  In any case,  do get involved and do keep an eye on it. You will be joining a lot of like-minded people and I expect there will be lots of new opportunities for the tools outside of education.

One of the really cool things is the transparency of the Efabless solution. You can see what works and doesn’t and even contribute to the fixes and become part of the evolution of the solution.  My MPMPW idea and my videos are just a couple of examples of a user adding value.

In your mind, how would the semiconductor supply chain benefit from this open-source movement?

I think that open-source will disrupt the traditional chip, tool and IP markets. Eventually, this will lead to a lot lower barrier to entry for new people to get involved and will lead to more people making more chips. I would imagine that, just like software, there will be winners and losers with the ones leveraging the movement reaping big benefits.

I’ve also heard about dramatic performance gains from designing special purpose SoCs for specific applications or using chiplets. I think both of these areas will be ones where the open-source tooling can compete on a more even footing by lowering the upfront cost or NRE, and focusing on community and simplicity.

In the case of domain specific accelerators,  open-source tools and frameworks make it easier to quickly build something. The LiteX example I gave earlier is a perfect example.

For chiplets, it allows the use of older and cheaper processes for digital IO or peripherals. These don’t need to be as performant in PPA terms, so why pay for the expensive tooling or use advanced nodes to develop them?

Then we have the security side, that’s always been something where open-source tooling is ahead. How can you trust the proprietary tools if you can’t inspect how they work. We have the same ‘more eyes’ reasoning that also makes sense for developing secure software and cryptographic algorithms.

Also read:

CEO Interview: Mike Wishart of Efabless

The Importance of Low Power for NAND Flash Storage

Security Requirements for IoT Devices

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