Maxim is a scientist, engineer, and entrepreneur. His expertise is in physics, mathematics, semiconductor devices, and EDA. Prior to co-founding Diakopto, Maxim worked at Apple’s SEG (Silicon Engineering Group), where he was responsible for parasitic extraction. Before Apple, he was CTO of Silicon Frontline Technology, where he architected and successfully brought to market several industry-leading tools such as R3D and Rmap. Maxim also worked as device engineer at PDF Solutions, T-RAM Semiconductor and Foveon. Prior to moving to the industry, he was a professor at Georgia State University and University of Aizu. Maxim graduated with a Ph.D. in Solid State Electronics from the Moscow Institute of Physics and Technology, and won the first place in the Physics Olympiads (USSR) for high schools and for universities.
Tell us about what Diakopto does and what prompted you to start the company.
Diakopto was founded to help chip designers, layout engineers and CAD teams solve IC problems caused by interconnects and layout parasitics. I saw first-hand the increasing pain and headaches that parasitics were causing, delaying tapeouts by weeks or months. It was agonizing for me to watch some of the smartest engineers attempting to solve parasitics-related IC problems using a manual, trial-and-error approach that was extremely tedious and time-consuming since none of the existing tools or methodologies were helping them find where the problems were, and what was causing them. They were largely shooting in the dark, trying different things to see if the problems went away. Or they would brute-force overdesign their chips to overcome these problems, which led to higher power, area and cost.
We wanted to equip these engineers with a flashlight and a magnifying glass, to give them insight and visibility into the parasitic effects and help them find the proverbial needle in a haystack. It was for this reason that we started Diakopto and why our first tool, ParagonX, became so successful so quickly.
Where does the name Diakopto come from and why did you pick it for your company?
It’s a twist on the word “Diakoptics” which was introduced by Gabriel Kron as a method for breaking a problem down into sub-problems which can be solved independently before being joined back together to obtain an exact solution to the whole problem. We take a very similar approach in our software and methodology to solve a very large problem by slicing it into smaller sub-problems to solve.
Diakopto is also the name of a beach-front vacation town in Greece (although I have not personally had the chance to visit).
Why has parasitics become such an important factor now? What changed?
A few factors have made parasitics the increasingly dominant challenge for engineers:
The main one is the industry transition to advanced technology nodes. In FinFET technologies, the number, magnitude and impact of parasitics on chip performance, power and reliability have grown exponentially. This not only considerably slows down simulations using existing tools (often taking many days to more than a week to complete), but if the simulations reveal problems, trying to debug the problems and find out which few parasitic elements (out of thousands, millions or billions) are causing the problems is a nightmare. This is where our tools and methodology come into play – to quickly and easily pinpoint the few parasitics that need to be fixed.
We also have many customers using our products and methodology in older technologies, such as 28nm, 40nm, 90nm, even 180nm. These customers are continually pushing the envelope of these older nodes in terms of speed, accuracy, linearity, etc. This moves their designs closer and closer to the edge of the cliff of those process nodes, where parasitics suddenly become critical.
Who are your competitors? What are the differences between Diakopto’s tools and other tools?
We believe that the shift from transistor-dominated designs (pre-FinFET) to parasitics-dominated designs has driven the urgent need for a new class of tools and methodology, developed from the ground up to analyze, visualize, debug and optimize parasitic effects in modern ICs. We have opened up a new market that is mostly untapped at this time.
We complement (and do not compete with) the major signoff tools such as SPICE simulators or IR/EM tools.
There are a couple of tools that claim to help with parasitics analysis, but they are not as versatile, fast or easy to use as ParagonX. Those tools will tell you there are problems, but they do not quickly and intuitively point to the root causes.
One of the big advantages of ParagonX is the ease-of-use and out-of-the-box experience it offers: there is no need for any setup or configuration, CAD support or foundry qualification. A novice user can start using the tool after a 10 minute training, which has been unheard of in the EDA industry until now. This is why it’s easy for our tool to proliferate to new design teams, layout engineers, and CAD groups.
Diakopto seems to have come out of nowhere, but already with over 30 companies using your debugging platform. What’s the backstory?
When we first introduced our ParagonX tool in 2018, we were pleasantly overwhelmed by the high level of interest from our early customers. And very quickly, the word spread to other engineers and other companies and we have more and more customers evaluating and signing up. We are pleased to see customers using ParagonX for different foundries, process nodes, design styles, and design applications: SerDes, image sensors, data converters, PLLs, memories, low-power IoT, AR/VR, wireless/RF and many more.
Again, having a tool that is designed for unparalleled ease-of-use and that requires virtually no training or support enables a rapid adoption of ParagonX across a broad section of the industry. Once our customers validated that this is indeed the case, we felt comfortable that we could broaden our reach to the thousands of semiconductor design teams out there that we have not yet tapped into and without compromising the user experience.
Where do you see Diakopto going from here?
We are very excited about our future. Not only have we seen the adoption of ParagonX grow exponentially over the last couple of years, we are also seeing a significant uptick in the frequency and expansion of use at our customer base. Many customers have embraced and made ParagonX part of their standard flow and methodology for IC design and debugging. We have a healthy pipeline of companies currently evaluating ParagonX and we believe they will soon join our global community of customers.
We are equally encouraged by the strong tailwinds that will continue to fuel our growth. There are several key market trends that driving the increasing need for our solutions:
- Hyperscale data centers
- 5G wireless
- IoT and sensors
- Autonomous vehicles
These market trends are in turn driving the need for (1) higher speed circuits, (2) higher precision circuits, and (3) broad industry migration to advanced process technologies – all 3 of which lead to the exponentially increasing severity of parasitic effects on chip PPA and time-to-market.
What makes me even more enthusiastic is the new products that we are bringing to market to address adjacent opportunities while staying rooted in our founding principles. We will be announcing some of the new products over the coming 12 months.
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