Ethernet speed evolution has kept a nice pace over the years even without any competing communications standard. And there are no signs of that slowing down, thanks to innovative companies deploying creative design techniques to keep delivering high-performance SerDes IP solutions. SerDes plays an integral role in implementing highspeed Ethernet connectivity.
The voracious appetite for high-speed data connectivity is driven by applications such as 5G, 4K on-demand video, audio streaming, photo sharing, IoT and AI deep learning. The hyperscale data centers supporting many of these applications and the “enterprise move to the cloud” initiatives play catalyzing roles in driving rapid adoption of the latest SerDes technologies in implementing Ethernet solutions. 112Gbps SerDes milestone was reached just in the recent past enabling easier implementations of 400G and 800G Ethernet connections.
Last month, at the DesignCon 2021 conference, Alphawave IP made a presentation titled “The Path to 200 Gbps Serial Links.” The presentation was authored by Tony Pialis (CEO) and Clint Walker (VP Marketing) and the talk given by Clint. Many of you know and/or have heard of Alphawave IP. They have been making waves recently in the wake of their IPO in a short span of four years from inception of the company. According to Dealogic, this is the largest semiconductor IPO in history.
What you may not know is that Tony is a serial entrepreneur, having founded three successful companies in the highspeed connectivity space. It is hard to believe that we were discussing 5Gbps not that long ago when I first met him and he is talking 224Gbps now. Okay, it was 15 years ago during his Snowbush days when I first met him. When most other solutions at that time were taking the all-analog route, Tony was talking DSP-based implementation. He was and still appears to be a firm believer in the scalability of that approach and the results speak for themselves. One of the many products that Alphawave IP offers is a 112Gbps Long-Reach (LR), low-power, DSP-based Multi-Standard-SerDes.
Knowing Tony, Alphawave IP doesn’t rest on its laurels. Right on the heels of launching their 112Gbps SerDes, they were off to the races, experimenting in their labs to achieve 224Gbps SerDes. The presentation at the DesignCon2021 was about their experimentation, their findings and predictions based on that. This blog will summarize the key points from that presentation.
Industry Adoption of Latest Connectivity Solutions
From a data center perspective, a move toward higher speed Ethernet connectivity promises not only power savings but also area savings thereby increasing interconnect densities. So, the industry is always eager to quickly adopt technologies that will help them move in that direction.
The above figure is loaded with useful information. The middle chart is very interesting to take a closer look. When a 200Gbps SerDes becomes available, 1.6TbE becomes possible. One with an 800GbE connectivity current offering can double their connectivity speed without changing the complexity of their design too much. Alternatively, they can maintain the 800GbE connectivity offering and reduce the complexity of their design. Either way, they get to enjoy the benefits of lower power of the next gen SerDes.
Challenge of Scaling to 224Gbps SerDes
Designs adopted PAM4 signaling to support data rates beyond 25Gb/s. But PAM4 signaling is much more sensitive to noise, reflections, non-linearities and baseline wander. Receiver design is much more complicated. Refer to figure below to see the stringent requirements on signal-to-noise (SNR) ratio and jitter spec to deliver 224Gbps SerDes. In order to drive reasonable channel lengths, insertion losses from packaging, board and cable need to be reduced in half.
Alphawave IP’s Experimentation
This presentation focuses on signal modulation experimentation to determine signaling scheme that will deliver 224Gbps rates. Alphawave IP considered 2-PAM, 4-PAM, 6-PAM, 8-PAM QPSK and 16-QAM modulation schemes for their experimentation. Higher modulation schemes introduce higher bit error rates (BER). In order to reduce BER to an acceptable 10-6 they had to improve SNR by 1-3dB. They tried advanced DSP detection to leverage Maximum Likelihood Sequence Detectors (MLSD) in achieving 1-3dB improvement in SNR. They were able to improve BER by two orders of magnitude.
After narrowing down their choices to PAM4 and PAM6 modulation schemes, they ran experiments with two different channels per modulation scheme.
As you see in the figure above, both the channels with the PAM6 modulation scheme delivered results that meet or exceed the requirements stated earlier. BER in the 10-6 range (or better) and SNR higher than 20.5. The PAM4 modulation scheme did not deliver.
Alphawave IP’s Findings
Alphawave IP’s conclusion is that PAM6 is a feasible modulation scheme for 224Gbps long-reach electrical transmission for channels used in this study. PAM4 will work for very short reach (VSR), medium reach (MR), chip to chip (C2C) and chip to module (C2M) electrical links. A total link solution that enables PAM4 for long reach channels is preferred.
If the industry as a whole can find a way to make PAM4 possible for a total link solution, that would be a big benefit for everyone involved. This calls for collaboration among different players within the ecosystem. For example, packaging, board and cable vendors working together with the goal of reducing insertion losses to enable longer channels. System vendors working toward reducing channel length requirements.
If the industry collaborative efforts don’t yield a total link solution at PAM4, PAM6 can be used to support channels where insertion loss deteriorates too rapidly.
If you’re part of the ecosystem involved with designing and deploying high-speed connectivity solutions, you would want to discuss more details with Alphawave IP.