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Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies

Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies
by Daniel Nenni on 02-08-2024 at 10:00 am
Categories: EDA, MZ Technologies

ANNA (1)

I spoke with Anna again at the Chiplet Summit this week, we had previously spoken at DAC 2023. MZ is short for Monozukuri which is a Japanese term that translates to “making things” or “manufacturing.” In a broader sense, it refers to the art, science, and craftsmanship of creating products which fit chiplets quite well.

Anna Fontanelli has more than 25 years of expertise in managing complex R&D organizations/programs to give birth to innovative EDA technologies. Fontanelli is an expert in IC/package co-design and led Monozukuri in the launch of GENIO, bringing a holistic design environment for 2D, 2.5D and 3D multi-component systems.

Tell us a little bit about yourself and your company.
I’m the Founder and CEO of Monozukuri, S.pA. who takes its products and services to market under MZ Technologies brand.  Our mission is to conquer 2.5D & 3D design challenges by delivering innovative, ground-breaking EDA software solutions and methodologies. Our technology redefines the co-design of heterogeneous microelectronic systems by providing an improved level of automation in three-dimensional interconnect optimization.

What was the most exciting high point of 2023 for your company?
We reached a huge milestone when an internationally respected System/ASIC company adopted our GENIOTM 1.7 fully-integrated EDA co-design tool.  They adopted a full-suite license and are targeting a next generation product family based on heterogeneous advanced system-in-package technology.

What was the biggest challenge your company faced in 2023?
People.  We are moving into a global expansion and are finding the availability of business development and account service pros who truly understand the needs of the marketplace are few and far between. We’re looking for people who are technically-sophisticated and sufficiently business savvy to help advanced technology IC companies take on their challenges.

How is your company’s work addressing this biggest challenge?
We’re recruiting like crazy.  We’re reaching out to industry contacts and we’re advertising on EDA websites.

What do you think the biggest growth area for 2024 will be, and why?
Clearly, Heterogeneous die integration challenges are going to do nothing but increase this year.  Yield, cost of design, and time-to-market are going to become paramount.

How is your company’s work addressing this growth?
We’re going to address some of most vexing advanced systems challenges: Helping designers deliver energy-efficiency improvement … that is performance per mW … and latency reduction.  We’re enabling a design approach that integrates signal and power integrity with thermal analysis for simulation-aware system interconnect optimization. This will allow technology-aware architecture exploration, 3D floor planning and system interconnect optimization to enable early up feasibility analysis without starting any physical implementation.

What conferences did you attend in 2023 and how was the traffic?
We attended DAC, where we had some very good exploratory meetings and we presented papers at DATE and the IEEE EDAPS 2023 Hybrid Conference. We’re not really worried about a lot of traffic per se. We offer a very specific value proposition, so the quality of the attendance is more important than the quantity.

Will you attend conferences in 2024? Same or more?
We’ll more than likely add Chiplet Summit to our conference attendance.

Additional questions or final comments?
2024 going to be all about chiplets, packaging and systems integration.  The most demanding IC systems today combine multiple components such as chiplets, memory and ASICs.  The package poses the challenge of handling, updating & optimizing complex interconnects in a 3D space. Present-day 3D chiplet architecture demands die stacking and silicon-to-silicon vertical communications capabilities using a mix-and-match “LEGO-like” assembly.  This new chiplet packaging requires new tools, new methodologies, and new flows.

Also Read:

CEO Interview: Anna Fontanelli of MZ Technologies

What ChatGPT has to say about the Chiplet Summit

Chiplet Summit 2024 Preview

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SOITEC Pushes Substrate Advantages for Edge Inference

SOITEC Pushes Substrate Advantages for Edge Inference
by Bernard Murphy on 02-08-2024 at 6:00 am
Categories: AI, Foundries, Soitec

FD SOI power min

You might not immediately see a connection between semiconductor substrate choices and inference at the edge. These technology layers seem worlds apart and yet SOITEC have a point. Edge AI has rapidly evolved from simple CNNs to now complex reinforcement learning systems and transformer based LLMs. Even when shrunk to edge footprints, these architectures are still very demanding in performance and power, challenging metrics for any edge device. Optimizing power especially requires dedicated investment all the way from architecture down to process. Product designers can’t afford to leave anything on the table, which means that the substrate on which circuits are built is just as important as other considerations.


The need for low power

There are many different types of intelligent edge device, but they uniformly need to run on little to no power. Edge devices commonly run on batteries or even without a battery, harvesting power from sunlight or ambient wireless energy. For consumer devices we expect to need to recharge every few days, but we don’t expect adding a smart voice command interpreter to push recharges to twice a day.

Conversely, we expect remote intelligent devices, for agriculture, grid, wildfire detection or infrastructure monitoring to be able to run for years before maintenance. Acceptable recharge rates for consumer devices would be completely unacceptable for remote or widely deployed IoT products .

AI in a car runs off the battery but now there are a lot more demands on those batteries from multiple ADAS sensors, intelligent entertainment options, navigation and driver monitoring systems. Adding to these multiple power demands cannot reduce a 300-mile range for an EV to 200-miles. Intelligent products must be as close as possible to invisible in the car power envelope.

And then there are competitive considerations. Inference AI is now commonly measured against inferences per watt per second. AI at the edge is a hugely competitive field so this metric must be optimized in every direction – inference rate (in frames per second for example) at the smallest possible power consumption.

The advantage of SOI technologies

I have written before about SiC substrates to enable power electronics for EVs and EV charging stations. SOITEC offerings also include SOI (silicon on insulator), POI (piezoelectric on insulator), and GaN (gallium nitride). Each builds on an insulation layer immediately below a thin semiconductor layer on which devices are patterned. This structure eliminates (or largely eliminates) the leakage through bulk silicon, a challenge which became limiting for mainstream semiconductor processes.

Other technologies have been developed, such as FinFET, to reduce leakage though in different ways. However those processes are more complex, resulting in higher wafer costs and therefore unit device costs.

Architects and firmware designers can also minimize leakage by turning off sections of a chip when not active. This method is effective, but design requires great care to ensure that dependencies between different aspects of functionality in the chip can be cleanly separated. If shortly after turning off a powered-down section it must turn on again to service some overlooked requirement, no power is really saved. Worse still, powering down and powering back up takes time, first in delays to turn off to allow time for dependent functions to complete. And later when turning back on to first recover to the same internal state in the function right before it powered down. All this overhead adds latency and reduces true performance for the device.

SOI technologies with inherently very low leakage can more fully exploit conventional sleep modes such as clock gating and DVFS than can non-SOI technologies. These techniques result in much simpler and lower latency demands on transitions between sleep and wake modes. And because the process is less complex than other advanced processes, SOI is intrinsically more efficient in inferences/watt/$.

Interested? You can learn more HERE.

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2024 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

2024 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
by Daniel Nenni on 02-07-2024 at 10:00 am
Categories: AMIQ EDA, EDA

AMIQ EDA DVT Eclipse

SemiWki has been working with AMIQ EDA for more than four years now and it has been quite the education. AMIQ EDA is a company that specializes in providing development and verification solutions for digital design and verification teams in the semiconductor industry. They offer a range of products and services aimed at improving productivity, efficiency, and quality in the design and verification process.

AMIQ EDA’s tools are widely used by semiconductor companies, design houses, and verification teams worldwide to streamline their development and verification processes, reduce time-to-market, and ensure the reliability of their designs.

Tell us a little bit about your company.
 We are an EDA company providing software tools targeting both chip design and chip verification. Our tools enable engineers to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology learning, improve testbench reliability, extract automatically accurate documentation, and implement best coding practices.

What was the most exciting high point of 2023 for your company?
As my co-founders mentioned in an interview with you in July, 2023 was the twentieth anniversary of AMIQ, consisting of AMIQ EDA and AMIQ Consulting. Although lots of great things happened last year, our celebration stands out the most. We have wonderful customers, and we are honored that they have been so supportive for more than two decades.

What was the biggest challenge your company faced in 2023?
There were really three challenges:

  • Continuing to provide strong customer support as our user base increased significantly
  • Maintaining quality as the number of our products, features, and use models grew
  • Hiring the right people to deliver on our product evolution, quality, and support

How is your company’s work addressing this biggest challenge?
For customer support, we’re investing in leveraged assets such as more intuitive user interfaces, more detailed documentation, and demo movies showing how to use our tools. We increased our investment in product quality by growing our QA team and enhancing our regression test suites. On the hiring side, we’ve found that an extensive internship program is a great way to find and train the best engineers.

What do you think the biggest growth area for 2024 will be, and why?
Our Design and Verification Tools (DVT) Integrated Development Environment (IDE) will remain our flagship product, but use of our other tools has been growing rapidly. Our Verissimo SystemVerilog linter has been widely adopted as people realize that the minimal code checking done by other tools is insufficient for enduring quality and correctness. We’re also seeing increased interest in our Specador documentation generator.

How is your company’s work addressing this growth?
We’re always adding more features to DVT IDE, in parallel on both the Visual Studio (VS) Code and Eclipse platforms. Verissimo is evolving at a rapid pace as we offer dozens of new rules every year, many of them suggested by our users. In addition, we have a major new release of Specador offering more ways to autogenerate high-quality documentation from user code.

What conferences did you attend in 2023 and how was the traffic?
We were glad to be able to return to in-person events last year. We exhibited at the Design Automation Conference (DAC) in the U.S., the Design and Verification Conference (DVCon) in the U.S. and Europe, and ChipEX in Israel. Traffic was generally quite good, although I doubt that we will ever get back to the “good old days” of bigger travel budgets and no pandemic concerns.

Will you attend conferences in 2024? Same or more?
At this point, we are planning to attend the same events. For us, conferences are less about generating new leads and more about connecting face-to-face with our users. We’re always prepared to show demos of new features and provide on-the-spot customer support. It’s great to see old friends and meet new ones, so I think that conferences will continue to be important for us.

Additional questions or final comments?
2023 was a truly great year for AMIQ EDA, and I have every expectation that 2024 will be outstanding as well. We’ll continue to be very busy enhancing our products and keeping up with new versions of the many standards we support. I’ll keep you updated with our regular chats. Thank you for the chance to share our thoughts.

Also Read:

Using Linting to Write Error-Free Testbench Code

AMIQ: Celebrating 20 Years in Consulting and EDA

A Hardware IDE for VS Code Fans

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Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells

Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells
by Fred Chen on 02-07-2024 at 6:00 am
Categories: Lithography

Application Specific Lithography

The discussion of any particular lithographic application often refers to imaging a single pitch, e.g., 30 nm pitch for a 5nm-family track metal scenario. However, it is always necessary to confirm the selected patterning techniques on the actual use case. The 7nm, 5nm, or 3nm 6-track cell has four minimum pitch tracks, flanked by larger width lines for ground and power rails. Figure 1 shows how a uniform 30 nm pitch exposure would lead to aggravated stochastic defect locations. When the illumination gives rise to fewer diffraction orders, a valley appears where we expect the rail peak, while image intensity imbalance occurs among the four inner trenches when more diffraction orders are included [1].

Figure 1. 30 nm pitch 6-track cell with exposed trenches (0.33NA EUV). The illumination angle (left) strongly affects both the optical image (center) and the expected stochastic defect location (right). The red circles indicate the stochastic defect hot spot locations.

When using a more absorbing metal oxide resist, unexposed trenches can be patterned. However, the aggravated stochastic defect locations are still present, and the image imbalance is worse, with pitch walking also evident (Figure 2).

Figure 2. 30 nm pitch 6-track cell with unexposed trenches (0.33NA EUV). The illumination angle (left) strongly affects both the optical image (center) and the expected stochastic defect location (right). The red circles indicate the stochastic defect hot spot locations. Red arrows indicate pitch walking (shift of peak positions).

The High-NA EUV system does not change the outcome [1], and is also not available. To avoid the above issues, the only one-mask solutions for patterning four 30 nm pitch tracks with the two large rails would be EUV Self-Aligned Double Patterning (SADP) and DUV Self-Aligned Quadruple Patterning (SAQP), starting with the same core cell pitch. The EUV-DUV difference of complexity and cost far exceeds the SAQP-SADP difference of processing complexity and cost, since SAQP has already long matured on mature tools [2,3]. The expected spacer layout and arrangement for the SAQP approach are shown in Figure 3.

Figure 3. Spacer layout and arrangement for DUV SAQP for the 6-track cell. The blue and red lines would be cut or trimmed separately.

The SAQP would then be followed by applying a cut mask at least twice, each time on alternating lines. The same dual cut mask approach has been applied as part of the well-known Self-Aligned Litho-Etch-Litho-Etch (SALELE) approach used with EUV, which uses four EUV masks in total [4]. The LELE EUV masks may also be substituted by DUV LELE with SADP at lower cost, though up to 4 extra DUV masks may be needed [5].

References

[1] F. Chen, “6-Track Cell Imaging in Low-NA and High-NA EUV Lithography,” https://www.youtube.com/watch?v=Z9MQuKrqLYw

[2] L-A. Ragnarsson et al., “The Environmental Impact of CMOS Logic Technologies,” 2022 EDTM.

[3] L. Liebmann et al., The daunting complexity of scaling to 7NM without EUV: Pushing DTCO to the extreme,” Proc. SPIE 9427, 942702 (2015).

[4] R. Venkatesan et al., Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node,” Proc. SPIE 12292, 1229202 (2022).

[5] F. Chen, https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen; F. Chen, https://www.linkedin.com/pulse/beol-mask-reduction-using-spacer-defined-vias-cuts-frederick-chen

This article first appeared in LinkedIn Pulse: Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells

Also Read:

Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography

Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM

Is Intel cornering the market in ASML High NA tools? Not repeating EUV mistake

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2024 Outlook with Thomas Gerner Nørgaard, Founder Comcores

2024 Outlook with Thomas Gerner Nørgaard, Founder Comcores
by Daniel Nenni on 02-06-2024 at 10:00 am
Categories: Comcores, IP

TGN Head View

SemiWiki has been working with Comcores for two years. They are very active in the semiconductor ecosystem and highly regarded.

Comcores specializes in providing digital intellectual property (IP) solutions and design services for communication and networking technologies. They focus on developing and delivering IP cores, which are pre-designed and pre-verified building blocks of digital systems, to help companies accelerate their product development in areas such as wireless communication, networking, and digital signal processing.

Comcores’ offerings often include IP cores for technologies like Ethernet, optical networking, 5G, and other communication standards. These cores are designed to be integrated into system-on-chip (SoC) solutions, helping companies reduce development time and costs while still meeting the requirements of modern communication systems.

Tell us a little bit about yourself and your company:
My name is Thomas Nørgaard, and I am a serial entrepreneur, with a keen interest in advanced technology. I founded Comcores in 2014, after my first venture Radiocomp. At Comcores, we are driven by creating technologies to enable the future. Our focus is to develop digital IP components & solutions that help reduce the barrier to developing new solutions by easy access to complex technology, lowering the total cost of integrating such functionality into new projects and providing the convenience of using a quality proven, interoperability tested and silicon agnostic solution.

What was the most exciting high point of 2023 for your company?
2023 was a very active and exciting year for us at Comcores. We worked on new complex projects within Time Sensitive Networking solutions and launched the new JESD204D IP. We are proud to be leading these areas and look forward to working with our customers in integrating these complex technologies.

What was the biggest challenge your company faced in 2023?
The continuous development of the TSN standards has been a difficult area to prioritize from a product development perspective for us. There are many standards and many profiles to account for and we want to make sure that our Ethernet switching solutions are meeting the latest profiles and features within this domain. Likewise, the software orchestration of these systems has been an area of intensive research.

How is your company’s work addressing this biggest challenge?
Comcores has launched multiple streams of development to meet the many profiles of TSN under development and has invested in expanding our teams with engineers having expertise in this field. To orchestrate these systems Comcores also has developed its first version of a Centralized Network Controller to handle the QoS policies in the TSN networks.

What are your expectations for 2024 and your plans for the trends?
2024 will hold a lot of exciting product launches that will contribute to anchoring our status as a leader of IP solutions in our respective areas. Ethernet Solutions is a particular area of interest where we will launch many new solutions with an enhanced content of software. Likewise, we will continue to launch support for new standards and features within JESD, Ethernet, MIPI and eCPRI. We have a lot to look forward to in 2024, and we see it being a fantastic year. We are perfectly poised to support our customers in developing their new solutions and help mature them.

About Comcores
We are a key supplier of digital IP Cores and solutions with a focus on Ethernet, Wireless and Chip-to-chip interfaces. We offer both  Stand-Alone IP components and Ethernet systems for ASIC & FPGA. Our solutions can be customized to meet your design specifications. By purchasing our IPs you drastically reduce your product cost, risk, and time to market. We enable you to focus on your competences.

We pride ourselves on providing the best-in-class, quality IP components and systems to ASIC, FPGA, and System vendors. Our core competence is the development and thorough validation of the IPs. 

Comcores, headquartered north of Copenhagen in Kgs. Our long-term background in mobile communication and being a first-mover in remote radio heads along with expertise in wireless networks gives us a solid foundation for understanding the complex requirements of modern communication tasks.

This know-how coupled with 40+ dedicated coworkers / employees/ professionals help us define and build state-of-the-art high-quality solutions.

Also Read:

WEBINAR: Understanding TSN and its use cases for Aviation, Aerospace and Defence

JESD204D: Expert insights into what we Expect and how to Prepare for the upcoming Standard

WEBINAR: O-RAN Fronthaul Transport Security using MACsec

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proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution

proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution
by Mike Gianfagna on 02-06-2024 at 6:00 am
Categories: Analytics, proteanTecs

proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution

proteanTecs is a unique company, delivering electronics visibility from within. Its core mission is to enable the electronics industry to continue to scale. The company achieves this goal by first embedding on-chip monitors, called Agents, during the design process to generate deep data on the chip’s profiling, health, and performance. Machine-learning algorithms process this on-chip data throughout the device’s lifecycle, in both test and mission modes. Users gain deep data analytics with actionable insights and alerts on a cloud-based platform with edge applications on the automated test equipment (ATE) or embedded on the board itself.

It’s well-known that power optimization is a huge and growing problem across many markets, so the application of this unique technology to this problem holds great promise. Read on to learn how proteanTecs is addressing the power consumption challenge.

Overview of the Power Reduction Solution

Recently, proteanTecs announced a new power reduction solution aimed at high-performance markets. Using its proven technology, chip makers and system operators can now optimize power and performance without the risk of system failure. This unique capability uses on-chip telemetry, machine learning and predictive analytics to enable workload-aware system-on-chip (SoC) power reduction during production testing and in-field operations. 

For in-field power savings, proteanTecs introduced AVS Pro™,  a real-time application for functional-workload aware adaptive voltage scaling (AVS). Based on timing margin Agents, AVS Pro leverages excessive guard-bands to reduce power while guaranteeing failure prevention. This capability is silicon-proven in leading-edge technologies and has enabled customers to reduce power consumption by an average of 8-14%.

For power reduction during production, proteanTecs offers prediction-based VDDmin optimization per individual chip and system, with deep data analytics for process grading. These applications are deployed on the tester with advanced analysis on the proteanTecs cloud platform. Partnering with leading ATE vendors, parametric power and performance visibility for inline decision making is enabled.

The technology finds application across a broad range of reliability-critical markets, such as cloud computing, mobile, telecommunications and automotive. The figure below provides an overview of how the pieces fit together.

Case Study of Use in a Real Design

Results in a real design project are the most compelling proof for any new optimization technology. proteanTecs has made a detailed case study available to demonstrate impact. Some key details and achievements disclosed in this case study include:

  • The customer is a fabless chipmaker making 5nm networking chips for datacenters
  • The challenge faced by this customer was high power consumption due to excessive voltage guard-bands
  • Using proteanTecs AVS Pro, power optimization with a safety-net was achieved in real-time
  • The result was a 12.5% dynamic power reduction which translates into more than $5M per year energy cost savings for hyperscale cloud vendors
  • An 11% performance increase was also achieved because of a higher utilization rate per system

There is more to this impressive story. You can download a complete copy of the case study here.

To Learn More about proteanTecs AVS Pro

Application-specific power performance optimization based on chip telemetry embodies many moving parts to realize the complete solution. The proteanTecs’ AVS Pro application monitors the margin to timing failure of millions of real paths, in real time, under real workloads, to reduce voltage to the lowest point that still allows error-free functionality. It also provides an inherent safety-net to prevent failures when events like voltage drops occur, while enabling fast frequency and voltage scaling.

The company has published a comprehensive white paper that dives into the details of how its technologies are combined to deliver these results. The piece covers the power, performance, reliability equilibrium that can be achieved with properly developed guard bands. The various approaches to dynamic power management are also discussed. The AVS Pro solution is explained in detail to illustrate how significant power reduction can be achieved. You can download your copy of this very informative white paper here.

Calculate Your Savings

If you visit the power reduction solution web page, there is a calculator to help you estimate the improvements that are possible for CPU, GPU and AI accelerator chips in the datacenter. If power optimization is a concern for a current or next design, I highly recommend you check out the savings that are possible. 

Also Read:

Fail-Safe Electronics For Automotive

Building Reliability into Advanced Automotive Electronics

Unlocking the Power of Data: Enabling a Safer Future for Automotive Systems

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2024 Outlook with Toshio Nakama of S2C

2024 Outlook with Toshio Nakama of S2C
by Daniel Nenni on 02-05-2024 at 10:00 am
Categories: EDA, Prototyping, S2C EDA
1 Comment

Precision Chip Strategy, PCS

Tell us a little bit about yourself and your company.
I am Toshio Nakama, the founder and CEO of S2C and a strong advocate of FPGA accelerated ASIC/SoC design methodology. I first started my career at Altera as an FAE and served in technical and sales management roles at Aptix Corporation. I co-founded S2C in Silicon Valley in 2003 and established R&D and manufacturing teams in Shanghai, China in 2004.

S2C is a leading global supplier of digital EDA solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions for 20 years.

With over 600 customers, including 6 of the world’s top 10 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer’s SoC and ASIC verification needs. S2C has offices and sales representatives in the US, Europe, mainland China, Hong Kong, Korea and Japan.

What was the most exciting high point of 2023 for your company?
Our 20th Anniversary! An exciting time for the company. Also, new products coming including OminiArk emulation, PegaSim simulation, and Claryti debugger

What was the biggest challenge your company faced in 2023?
New applications  and new technologies are coming quickly. In terms of new applications, the industry is experiencing growth in various areas, including market expansion and the emergence of technologies like RISC-V, Chiplet, and AI. New technology trends, including fresh architectures, evolving standards, changing requirements, and innovative ideas, continue to push the industry ahead.

How is your company’s work addressing this biggest challenge?
Delivering solutions tailored to meet customer demands for new technologies and applications. Collaborating with environmentally conscious partners to create a mutually beneficial ecosystem.

What do you think the biggest growth area for 2024 will be, and why?
New applications and technologies will be the primary growth area in 2024. Chiplets and AI specifically and newly developed IP such as RISC-V and the many variations. We are also seeing growth in the ARM ecosystem. With software being a barrier for systems companies prototyping is even more important so software can be developed in concert with hardware. 2024 will definitely be a growth year.

How is your company’s work addressing this growth?
The recently introduced S2C Precision Chip Strategy:

Heterogeneous verification method accelerates large-scale digital circuit, boosting user productivity. By seamlessly combining various products line, S2C empowers designers to tackle complex challenges more efficiently, ultimately leading to more robust and optimized designs cyclical.

Parallel Drive & Shift-left Method. S2C assists our valued customers in two crucial aspects of their projects: designing the right chip and designing the chip right.

What conferences did you attend in 2023 and how was the traffic?
We were very active in conferences around the world. DAC and DVCon are a long tradition with our company. We are also participating in RISC-V conferences and other regional events. In 2024 we expect even more conference activity around the world with much higher attendance. It should be a very big growth year for S2C and the semiconductor industry.

Final Comment?
Thank you very much for this opportunity. SemiWiki  is a valued partner we look forward to seeing you again at DVCon Next month.

Also Read:

Prototyping Chiplets from the Desktop!

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

ViShare’s Rapid Market Entry with FPGA-Based Prototyping Solution from S2C

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Expedera Proposes Stable Diffusion as Benchmark for Edge Hardware for AI

Expedera Proposes Stable Diffusion as Benchmark for Edge Hardware for AI
by Bernard Murphy on 02-05-2024 at 6:00 am
Categories: AI, Expedera, IP

Stable diffusion image min

A recent TechSpot article suggests that Apple is moving cautiously towards release of some kind of generative AI, possibly with iOS 18 and A17 Pro. This is interesting not just for Apple users like me but also for broader validation of a real mobile opportunity for generative AI. Which honestly had not seemed like a given, for multiple reasons. Finding a balance between performance and memory demand looks daunting for models baselining at a billion or more parameters. Will power drain be a problem? Then there are legal and hallucination issues, which perhaps could be managed through carefully limited use models. Despite the apparent challenges, I find it encouraging that a company which tends to be more thoughtful about product releases than most sees a possible path to success. If they can then so can others, which makes a recent blog from Expedera enlightening for me.

A quick recap on generative image creation

Generative imaging AI is a field whose opportunities are only just starting to be explored. We’re already used to changing our backgrounds for Zoom/Google Meet calls, but generative AI takes this much further. Now we can re-image ourselves in different costumes with different features in imaginary settings – a huge market for image-conscious consumers. More practically, we should be able to virtually try on clothing before we buy or explore options when remodeling a kitchen or bathroom. This technology is already available in the cloud (for example Bing Image Creator) but with all the downsides of cloud-based services, particularly in privacy and cost. Most consumers want to interact with such services through mobile devices; a better solution would be local AI embedded in those platforms. Generative AI through the open-source Stable Diffusion model is a good proxy for hardware platforms to serve this need and more generally for LLM models based on similar core technologies.

Can on-board memory and performance be balanced at the edge?

First, we need to understand the Stable Diffusion pipeline. This starts with a text encoder to process a prompt (“I want to see a pirate ship floating upside down above a sea of green jello”). That step is followed by a de-noising neural net which handles the diffusion part of the algorithm, through multiple iterations creating information for a final image from trained parameters. I think of this as a kind of inverse to conventional image recognition, matching between prompt requirements and the training to create a synthesized match to the prompt. Finally a decoder stage renders the image from the data constructed in the previous step. Each of these stages is a transformer model.

The Expedera blog author, Pat Donnelly (Solutions Architect), gives a detailed breakdown of parameters, operations and data moves required throughout the algorithm which I won’t attempt to replicate here. What stood out for me was the huge number of data moves. Yet he assumes only an 8MB working memory based on requirements he’s seeing with customers rather than optimal throughput. When I asked him about this, he said that operation would clearly depend on a DDR interface to manage the bulk of this activity.

This is a switch from one school of thought I have heard – that model execution must keep everything in local memory to meet performance requirements. But that would require an unreasonably large onboard SRAM. DRAM makes sense for handling the capacity, but another school of thought suggests that no one would want to put that much DRAM in a mobile device. That would be too expensive. Also slow and power hungry.

DRAM or some other kind of off-chip memory makes more sense but what about the cost problem? See the above reference on Apple. Apparently they may be considering flash memory so perhaps this approach isn’t so wild. What about performance? Pat told me that for Stable Diffusion 1.5, assuming an 8K MAC engine with 7 MB internal memory and running at 750 MHz with 12 GBps external memory bandwidth, they can process 9.24 images/second through the de-noiser and 3.29 images/second through the decoder network. That’s very respectable consumer-ready performance. Power is always tricky to pin down since it depends on so many factors, but numbers I have seen suggest this should also be fine for expected consumer use models.

A very useful insight. Seems like we should lay to rest the theory that big transformer AI for the edge cannot depend on off-chip memory. Again you can read the Expedera blog HERE.

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What ChatGPT has to say about the Chiplet Summit

What ChatGPT has to say about the Chiplet Summit
by Daniel Nenni on 02-04-2024 at 12:00 pm
Categories: AI, Chiplet, Events
1 Comment

Chiplet

Quite a few of the articles I now see about the semiconductor industry use AI. It is not hard to tell, especially for someone like myself, a 40 year experienced semiconductor professional who also writes. In the last 13 years (yes SemiWiki is now a teenager) we have published 9,058 blogs. SemiWiki was the first of now many semiconductor blogging sites and it is an honor to work with so many talented people on both sides of the table.

I already did a post on the Chiplet Summit but since chiplets are the next big semiconductor thing I thought it would be fun to see what ChatGPT had to say.

ChatGPT: Write and article about the Chiplet Summit:

Exploring the Future of Semiconductor Innovation: A Recap of the Chiplet Summit

Introduction: The technology landscape is constantly evolving, and one of the key drivers behind this evolution is the semiconductor industry. In recent times, a groundbreaking concept has been gaining traction in the semiconductor community – chiplets.  of chiplets in shaping the future of semiconductor design.

Understanding Chiplets: At its core, a chiplet is a modular component of a semiconductor design that serves a specific function. Rather than creating monolithic chips that encompass all functionalities, chiplets allow for the assembly of smaller, specialized components into a cohesive system. This modular approach has the potential to revolutionize the semiconductor industry by offering greater flexibility, scalability, and efficiency in the design and manufacturing processes.

Key Themes Explored at the Chiplet Summit:
  1. Interoperability and Standardization: One of the primary discussions at the Chiplet Summit revolves around establishing standards for chiplet design and interoperability. Creating a common framework ensures that chiplets from different manufacturers can seamlessly integrate into a single system. Standardization not only simplifies the design process but also encourages collaboration among industry players.
  2. Scalability and Customization: Chiplets pave the way for scalable semiconductor architectures, allowing designers to mix and match components based on specific application requirements. This scalability enables the creation of highly customized solutions for various industries, from consumer electronics to data centers. Attendees at the summit explore the potential applications and advantages of scalable chiplet architectures.
  3. Economic and Environmental Impacts: Chiplets have the potential to significantly reduce the economic and environmental costs associated with semiconductor manufacturing. By reusing proven chiplet designs across different products, manufacturers can streamline their production processes and minimize waste. The summit addresses how chiplets contribute to a more sustainable and cost-effective semiconductor ecosystem.
  4. Innovations in Integration Technologies: The Chiplet Summit serves as a showcase for the latest advancements in integration technologies. From advanced packaging techniques to novel interconnect solutions, participants explore the cutting-edge technologies that enable seamless integration of chiplets. These innovations play a crucial role in realizing the full potential of chiplet-based designs.
  5. Challenges and Solutions: While chiplets offer tremendous opportunities, they also present challenges, such as ensuring robust communication between chiplets, managing thermal issues, and addressing security concerns. The summit provides a platform for experts to discuss these challenges and collaboratively work towards viable solutions.

Conclusion: The Chiplet Summit stands at the forefront of semiconductor innovation, bringing together visionaries and thought leaders to explore the vast potential of chiplet technology. As the industry continues to embrace this modular approach to semiconductor design, the summit plays a pivotal role in shaping the future of electronics. With ongoing advancements and collaborative efforts, chiplets are poised to revolutionize the way we perceive and create semiconductor devices, unlocking new possibilities for technological innovation.

End:

In my opinion AI will in fact replace most of the people who write “popular”  semiconductor articles because ChatGPT in effect does what they do, re hash what has already been written. SemiWiki bloggers however share their semiconductor experience, observations, and opinions so we are safe, for now.

Also Read:

Chiplets Open Pandora’s Box

How Disruptive will Chiplets be for Intel and TSMC?

Will Chiplet Adoption Mimic IP Adoption?

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

Podcast EP206: An assessment of the Chiplet Ecosystem Movement with Alphawave’s Tony Chan Carusone

Podcast EP206: An assessment of the Chiplet Ecosystem Movement with Alphawave’s Tony Chan Carusone
by Daniel Nenni on 02-02-2024 at 10:00 am

Dan is joined by Tony Chan Carusone, Chief Technology Officer of Alphawave Semi. Tony has been a professor of Electrical and Computer Engineering at the University of Toronto since 2001 and has served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society and on the Technical Program Committees of the world’s leading circuits conferences.

He co-authored the classic textbooks “Analog Integrated Circuit Design” and “Microelectronic Circuits” and he is a Fellow of the IEEE. Tony has also been a consultant to the semiconductor industry for over 20 years, working with both startups and some of the largest technology companies around the world.

Dan and Tony discuss the emerging movement toward a chiplet ecosystem. Tony describes some of the significant benefits of this approach, including ease of prototyping, power reduction and achieving density beyond the reticle limit. The flexibility offered by a chiplet ecosystem and the ability to more easily integrate optical interconnect are also discussed.

Tony describes Alphawave’s commitment to building a chiplet ecosystem, the technology and products that the company offers and an assessment of what the future holds. He offers a realistic view of how the chiplet ecosystem will mature that is based on past achievements in the industry.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.