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Developing Effective Mixed Signal Models. Innovation in Verification

Developing Effective Mixed Signal Models. Innovation in Verification
by Bernard Murphy on 10-30-2023 at 6:00 am

Mixed-signal modeling is becoming more important as interaction between digital and analog circuitry become more closely intertwined. This level of modeling depends critically on sufficiently accurate yet fast behavioral models for analog components. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

Mixed Signal Models

The Innovation

This month’s pick is Fast Validation of Mixed-Signal SoCs. The paper was presented in the 2021 Journal of the Solid-State Circuits Society. The authors are from Stanford, Seoul National University and Scientific Analog.

A recent SemiWiki blog on mixed signal captured enormous interest, suggesting this is an area worth further study. A critical step to realize effective mixed signal verification is to develop accurate mixed-level behavioral models for analog functions which are suitable for event-driven simulation, and even synthesizable models for deployment in hardware emulation. The paper describes a template-based approach to generating models and two methods to interpolate analog behavior to event-based connections: oversampling and event-driven modeling with feature vectors (real number models).

The authors demonstrate application to a high-speed link simulation and emulation with impressive results. Comparison between Spice and Verilog simulation on the ADC shows close correspondence in results, running orders of magnitude faster. Emulation-based modeling adds yet more orders of magnitude to that speed.

Paul’s view

Big context-swap this month into the world of analog verification and its “mixed-signal” intersection with digital verification. This paper is an invited paper in a prestigious journal which beautifully summarizes state-of-the-art to build abstracted models of analog circuits that can keep up with digital simulation, even on an emulator, and do so with amazingly good accuracy.

In the analog world everything is smooth and usually oscillating, with intended input-output behavior often described by first transforming input/output waveforms into the frequency domain. The gold standard for analog simulation is Spice, iteratively solving device-level differential equations for voltages at all points in a circuit within guaranteed error tolerances. Compared to digital simulation, Spice is thousands of times slower.

The typical approach to creating fast abstract analog models is to do discrete time sampling of the input waveform and then generate the appropriate discrete time sampled output waveform using some DSP-like logic (e.g. discrete-time filters). Signal values between these discrete time points can be generated if needed using linear or spline-based interpolation.

The authors present a complete open-source framework with an elegant model generation language and compiler to generate both simulatable and emulatable models from this language. They use an adaptive time-step sampling method with spline-based interpolation and work through a credible case study using their framework on a 16nm high speed SERDES link PHY. Going from Spice to digital CPU-based simulation with their abstracted models achieves a 13,000x speed-up. Putting the models on an FPGA gave another 300x speed-up. Nice.

Raúl’s view

The validation of mixed-signal SoCs is a challenge, among other things because running sufficient test vectors to validate the digital parts – typically with an event driven simulator or on an emulator – results in prohibitive times to simulate the analog part with a circuit simulator. A solution is the creation of analog behavioral models. This month’s paper reviews several approaches to create these models and presents what the authors believe to be the first complete, open-source framework for AMS emulation. This is an invited paper to the IEEE open journal of the Solid-State Circuits Society, and as such large passages read like a tutorial on analog design and validation. It is quite different to what we have done before in this blog; the reader needs some analog know-how to be able to fully benefit (e.g., Laplace domain, z-transform, PLL, phase interpolator, Nyquist rates, jitter, etc.).

Functional models of analog circuits receive inputs and generate outputs at discrete times. Waveforms can be modelled using piecewise constant or piecewise linear functions, using spline points (the approach used in this paper) or sums of complex exponential functions. Time is modelled as discrete-time (sampled or oversampled) or as piecewise linear modeling (used here). The actual models of circuits are assembled from a library of templates. The authors put all this together in a system consisting of: 1) A Python tool for generating synthesizable AMS models providing a set of functions that allows users to describe AMS blocks as differential equations, netlists, transfer functions, or switched systems, … in either fixed or floating point, and 2) A simulator-like abstraction of FPGA boards.. which provides emulation infrastructure that manages the emulation timestep, emulation clock speed, and test interfaces and generates the FPGA emulation bitstream with the help of EDA tools.

The trick is not using circuit simulation but rather replacing circuit models by functional models. For a high-speed link receiver called DragonPHY the speedup of a Verilog versus a Spice simulation is 12,800x, providing sufficient accuracy. But even this speedup is not enough to simulate the clock recovery and channel equalization loops, to test bit error rates (BER), with feedback loops which may take 100,000s of cycles to settle. Modifying the models so they are synthesizable and can be incorporated into emulation provides further 5000x speedup, sufficient to compute BER within 7.5%. Impressive!

Also Read:

Assertion Synthesis Through LLM. Innovation in Verification

Cadence Tensilica Spins Next Upgrade to LX Architecture

Inference Efficiency in Performance, Power, Area, Scalability

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