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Breker Brings RISC-V Verification to the Next Level #61DAC

Breker Brings RISC-V Verification to the Next Level #61DAC
by Mike Gianfagna on 07-09-2024 at 6:00 am
Categories: Breker Verification Systems, EDA, Events

DAC Roundup – Breker Brings RISC V Verification to the Next Level

RISC-V is clearly gaining momentum across many applications. That was quite clear at #61DAC as well. Breker Verification Systems solves challenges across the functional verification process for large, complex semiconductors. Its Trek family of products is production-proven at many leading semiconductor companies worldwide. So, it seems logical that Breker brings RISC-V verification to the next level and that’s exactly what the company did at #61DAC.

The highlight of Breker’s presence at the show includes:

  • A complete range of tests for the entire RISC-V core verification stack from ISA to system-level interaction and performance.
  • Test Suite Synthesis AI Technology to track complex, unpredictable bugs and accelerate coverage of complex, super-scalar, out-of-order microarchitecture pipeline implementations
  • Self-checking content that is portable across simulation, emulation, and post silicon with debug and coverage analysis

Let’s look at how Breker brings RISC-V verification to the next level.

RISC-V Automated Core Verification with Synthesis Amplification

Common RISC V Verification Stack

The verification of a RISC-V processor core should include a “stack” of scenarios as shown in the figure. Breker’s RISC-V CoreAssurance SystemVIP uniquely provides this complete scenario range. A complete range of tests for the entire RISC-V core verification stack is provided. Starting with randomized instruction generation and microarchitectural scenarios, unique tests are provided that check all integrity levels, ensuring the smooth application of the core into an SoC.

This can also be extended to allow custom RISC-V instructions to be fully incorporated into the complete test suite. The capability may be ported across simulation, emulation, prototyping, post-silicon, and virtual platform environments to complete the picture.

A capability called test suite synthesis verification amplification is also included. Most test suites are templated in nature, allowing individual tests to be configured for various design situations. Using Planning Algorithms, an AI technique, Breker’s SystemVIP is based on synthesis technology that has an amplifying effect on the scenario models to significantly improve coverage and bug hunting.

Comprehensive System Coherency Verification

Breker’s popular Cache Coherency SystemVIP is used by most of the leading semiconductor companies worldwide to find hundreds of bugs over many complex SoCs. As the complexity of SoCs increases, so does the requirement for system level coherency that includes fabric and I/O, as well as advanced memory architectures.

Breker addresses these challenges with its next generation System Coherency SystemVIP, leveraging Test Suite Synthesis to generate a broad range of coherency tests. These tests are based on multiple verification algorithms and may be easily configured to operate on all memory and fabric architectures across multicore platforms. The synthesis platform includes AI planning algorithms, cross combination and concurrent scheduling for high-coverage, and complex corner-case evaluation.

As more complex RISC-V multi-cores and systems are produced, coherency for these designs is increasing in importance. Breker’s coherency SystemVIP works hand-in-hand with its other RISC-V SystemVIPs to enable a complete solution for the most advanced designs.

The SystemVIP can generate both C code and transactions for SoC testbenches, or UVM sequences for cache unit and sub-system simulation. It can operate on a virtual prototype, simulation, emulation, FPGA prototype and even actual silicon platforms, and includes full debug and profiling of the device under test on those platforms.

Breker’s Test Suite Synthesis has been shown to produce dramatic improvements in test composition time and coverage over and above basic test generators, including typical templating test schemes. The figure below provides an overview of the platform.

Platform Overview

The CEO Perspective

Dave Kelf

I had the opportunity to catch up with my good friend and CEO at Breker, Dave Kelf. I wanted to get his perspective on RISC-V market and the impact these new innovations from Breker are having. Here’s what Dave had to say:

While RISC-V represents a huge discontinuity across the electronic industry, there is a quality expectation that has been set by companies such as Arm that RISC-V cores must meet to be successful. This requires in-depth, comprehensive verification, and the best way to meet at least part of this need is to reuse test suites that are already proven.

RISC-V verification has its unique challenges, and these are compounding as the cores get more advanced. Existing, templated tests are fine for basic embedded cores, but run out of steam for the types of devices that are now emerging. We need to apply synthesis techniques to tease out deep sequential, unpredictable bugs, implement performance-based testing and enable system-level integration verification, and this accounts for the demand explosion we have seen at Breker.

To Learn More

You can learn more about RISC-V automated core verification with synthesis amplification here and you can learn more about comprehensive system coherency verification here.  And that’s how Breker brings RISC-V verification to the next level at #61DAC.

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Intel’s Gary Patton Shows the Way to a Systems Foundry #61DAC

Intel’s Gary Patton Shows the Way to a Systems Foundry #61DAC
by Mike Gianfagna on 07-08-2024 at 10:00 am
Categories: 3D IC, Events, Foundries, Intel Foundry
5 Comments

DAC Roundup – Intel’s Gary Patton Shows the Way to a Systems Foundry

#61DAC was buzzing this year with talk of AI and multi-die, heterogeneous design. The promise of making 2.5/3D design and a chiplet ecosystem mainstream reality was the focus of a lot of the panels and presentations at the conference. AI is certainly a driver for this new design style, but the conversation was broader than just AI, as you will see. This new design style will require effort from every part of the semiconductor ecosystem, and this focus was on display during DAC. There is a focal point where all this work needs to come together to make it commercially available. That focal point is the foundry, and there was a keynote address on Tuesday morning at DAC that did a great job explaining how to open the door to the future. Let’s explore how Intel’s Gary Patton shows the way to a systems foundry.

What a Systems Foundry Is and Why It Matters

Before I get into Gary’s keynote, I’d like to address the elephant in the room. I’ve been in the semiconductor business for a very long time. Over the years, I’ve known Intel as a technology powerhouse that dominates markets, crushes the competition and does things the Intel Way.

Open, collaborative, ecosystem-focused and service-oriented weren’t necessarily the first things I would think of when I heard “Intel”. But that’s exactly the presentation delivered by Dr. Gary Patton during his keynote address. Intel is clearly changing, and in a big way. With its systems foundry initiative, Intel is taking a leadership role in defining the future of semiconductor design and manufacturing. This role requires a new type of culture, and Gary is one of the Intel executives that is leading way. I had a chance to speak 1:1 with Gary at DAC, and I’ll share some of his personal insights in a moment. But first, let’s look at some of the messages from his keynote.

Gary began with some eye-opening statistics. According to IDC, the world creates nearly 270,000 petabytes of data every day. That’s 270,000,000,000 gigabytes. Intel estimates that by 2030, 1 petaflop of compute and 1 petabyte of data will be less than 1 millisecond away from the average user. Enabling these achievements will require disruptive innovation – innovation that clearly goes beyond the Moore’s Law scaling we’ve come to rely upon for so long.

He also mentioned that while AI is contributing to this huge growth in data volume and data processing requirements, it also presents significant energy efficiency challenges. According to the NY Times and Google, AI could soon need as much electricity as an entire country (~100 terawatt-hours/year).

Gary pointed out that disruptive innovation is nothing new to our industry. Over the years, we’ve conquered the bipolar power limit, gate oxide limit, and now the planar device limit. Conquering this last one will require a combination of chip and chiplet implementation as well as package interconnect density and energy efficiency. Intel aims to be at the epicenter of all these innovations and that’s what its Systems Foundry initiative is all about.

Thanks to its advanced packaging work, Intel is on track to deliver a 50X improvement in energy efficiency and a 10,000X improvement in interconnect density, as shown in the figure below.

Intel Packaging Innovation

Gary looked beyond Intel’s innovations for the complete picture. He discussed the work of UCIe, a consortium of 135 companies. The stated goal of this effort is to develop an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. Gary explained that the work of UCIe is delivering two orders of magnitude improvement in energy efficiency and three to four orders of magnitude improvement in bandwidth when compared with the standard package in the lower left of the figure above. These packaging improvements also deliver at least one order of magnitude lower latency than external interconnects like PCIe, Ethernet etc.  This is important work that Intel Foundry is clearly supporting.

Gary then discussed the importance of system technology co-optimization, a much broader and more ambitious version of design technology co-optimization. He explained that software & architecture, packaging, and silicon are all part of this effort which must be holistic. He stated that, “progress at individual layers in the stack is necessary but not sufficient. The entire system must be co-optimized. “

While much of the advanced process and packaging work at Intel is fueling this effort, close collaboration with the entire IP, EDA, design services, and advanced system assembly and test ecosystem is also critical for success. He described in detail the many programs that Intel Foundry has underway with its ecosystem partners to build and certify next-generation design and manufacturing capabilities.  He described regular meetings with all key EDA suppliers and showed very detailed scorecards of EDA certifications across all key Intel technologies. The breadth of this effort is truly impressive.  Coming a bit later in this post is more proof of Intel’s commitment to an open design flow.

Gary described the five-year investment Intel has made to deliver a systems foundry capability. He reported that today the company has over 100 2.5D designs in manufacturing. Design enablement, an open and collaborative attitude with a quality-first culture and strong customer support and certified methodologies are all part of this investment as shown in the figure below.

Intel Investment

The chart above really drove it home for me. This is very much a new and improved version of Intel. One that maintains its technology strengths but adds all the elements of a leading, world-class foundry to create a systems foundry. Next, let’s get to know the presenter of the keynote.

Leading Change – Gary Patton’s Perspective

Gary Patton

I was fortunate to have some private time with Gary after his keynote at DAC. Gary is one of the many “outsiders” that Intel has hired over the past few years – that five-year investment that is summarized above. I believe Gary’s entire career prepared him for his current work at Intel. After receiving his Ph.D. in EE from Stanford, he spent over 25 years in various leadership roles at IBM, in research, microelectronics and various corporate initiatives and product lines. Throughout this time, he honed his skills in product/technology development as well as ecosystem collaboration.

He then spent 4.5 years at Globalfoundries as chief technology officer and senior vice president of Worldwide R&D and Design Enablement. He has now been at Intel for 4.5 years as corporate vice president and general manager, Foundry Design Enablement. He is one of the many recent hires at Intel who bring broad industry experience to the company. 

Gary explained that he has always had a great respect for the accomplishments of Intel. He came to the company not to “fix” anything, but rather to take a great company to the next level. It seems to have worked out well. He credits the past 4.5 years as the best time in his career. When you consider all the things he’s accomplished, that’s saying a lot.

Gary talked about a corporate-wide shift at Intel to address the broader challenges and opportunities ahead.  Tone at the top is an important part of this and Pat Gelsinger is exactly the right person to convey those messages. Gary is delightful to speak with. He is articulate, personable and a very effective leader. A closing comment he made sticks with me. He explained that he brought many lessons learned to Intel from his prior experiences. A key one is that, “if you’re in the foundry business, your customers will make you better.”

Proof of Intel’s Commitment to An Open Design Flow

On the first day of DAC there was more proof of Intel’s growing ecosystem and the commitment being made to create a broad set of reference flows. The following announcements were made by Intel ecosystem partners to support access to Intel’s EMIB technology:

  • Ansys is collaborating with Intel Foundry to deliver signoff verification of thermal and power integrity and mechanical reliability of Intel’s EMIB technology spanning advanced silicon process nodes to various heterogenous packaging platforms.
  • Cadence announced the availability of a complete EMIB 2.5D packaging flow, digital and custom/analog flows for Intel 18A, and design IP for Intel 18A.
  • Siemens announced the availability of an EMIB reference flow for Intel Foundry’s customers. This is in addition to their announcement of Solido™ Simulation Suite certification for custom IC verification on Intel 16, Intel 3, and Intel 18A nodes.
  • Synopsys announced the availability of its AI-driven multi-die reference flow for Intel Foundry’s EMIB advanced packaging technology, accelerating the development of multi-die designs.

Suk Lee, vice president for Ecosystem Development at Intel Foundry commented, “today’s news shows how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI systems ambitions.”

You can see the complete announcement from Intel Foundry here. You can learn more about Intel’s plans to deliver a systems foundry for the AI era here.  And that’s some backstory about how Intel’s Gary Patton shows the way to a systems foundry.  #61DAC

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My Experience #61DAC

My Experience #61DAC
by Daniel Nenni on 07-08-2024 at 6:00 am
Categories: 3D IC, EDA, Events

Needham DAC

The theme of this year’s DAC was Chips to Systems which is a full circle type of thing since systems companies used to make their own chips. Old school computer companies were the biggest chip makers when I started  in the semiconductor industry. IDMs like Motorola and Intel replaced them at the chip level. Shortly after I joined the industry a start-up company (Sun Microsystems)  put HPC on our desktops with the slogan “The Network is the Computer” and changed computing forever.

Following Apple, other systems companies took control of their silicon with the likes of Tesla, Google, Amazon, Microsoft, and many others who make chips for internal use only. More than half of the traffic on SemiWiki is now from systems companies which is a big shift to the left.

So, Chips to Systems is a good DAC theme for sure but AI was the most referred to acronym at the conference. We do love our acronyms, absolutely.

I don’t know the official attendance numbers but I would bet #61DAC traffic was much higher than last year. However, given that we’ve had 21 consecutive quarters of positive growth for total EDA revenue, you would think DAC attendance would be much higher. If DAC was held at the San Jose Convention Center, which it never has been, I would expect the attendance numbers to double, my opinion.

There was certainly a different mix of companies on the exhibit floor. Some of the large EDA companies are less supportive of DAC but many new companies have replaced them which is a very good thing.

The big take-away from DAC for me this year is the depth of experience inside the ecosystem. I asked just about everyone I spoke with when their fist DAC was thinking I would win since mine was 1984 in Albuquerque NM. The winner was 1978 back in the RCA electronics days before there were exhibits.

DAC opened with the usual Sunday night networking party and the opening keynote from Charles Shi from Needham. Charles is the best qualified analyst I know. He has a Ph.D. in Material Science plus an MBA from UC Berkeley and he spent 5 years at Applied Materials before switching sides to analyst. Charles is very approachable and EDA is VERY lucky to have him. I would suggest to the DAC Committee that Charles speak first thing Monday morning in the DAC Pavilion for all to see.

Charles rightly pointed out that Nvidia really is the only company that has cashed in on the AI surge thus far which echo’s one of my concerns that the AI infrastructure spend is by far outrunning actual AI profits.  This points to a bubble. If so, I just hope we prepare and have a soft landing.

Charles is right, the semiconductor industry is transforming once again, going back to where it all started. TSMC helped enable this systems company shift by integrating packaging into the foundry business and now Intel and Samsung are following suit. The interesting thing about Samsung is that they are a systems company. In fact, Samsung is one of the largest and most experienced electronic systems companies in the world. Intel has already laid claim to being a “Systems Foundry” so that is a lost opportunity for Samsung.

The foundry landscape certainly has changed since Intel re-entered the market. Samsung is now between two very big dogs eating out of the same bowl. Just like EDA back in the day. TSMC is the trusted foundry with the massive ecosystem of customers, partners, and suppliers. Intel is the Systems Foundry which is explained in our next blog: Intel’s Gary Patton Shows the Way to a Systems Foundry. Gary started at IBM in 1986 after completing his Ph.D. at Stanford. As I said, the depth of experience at DAC is amazing.

As I mentioned previously, I moderated a DAC panel on 3D IC. One of the panelists was Rob Aitken (Ph.D. from McGill University). Today Rob is Program Manager, National Advanced Packaging Manufacturing for the U.S. Department of Commerce (CHIPs Act). Previously he was at Synopsys and ARM. I first met Rob at Artisan 20 years ago, before the Arm acquisition, and many times after that. Rob’s special talent is explaining the most complex technologies in ways that even I can understand. On the panel he reduced the complexities of 3D IC down to making a sandwich…

Our #61DAC coverage will continue through this month so stay tuned…

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Podcast EP234: An Update on Chips and Science Act Progress with Mike O’Brien

Podcast EP234: An Update on Chips and Science Act Progress with Mike O’Brien
by Daniel Nenni on 07-05-2024 at 10:00 am

Dan is joined by Mike O’Brien. Mike was recently the vice president of aerospace and government at Synopsys, He has 40 years of experience in the semiconductor, software and computer industries. In his 27 years in EDA and IP at Synopsys and Cadence, Mike helped build new lines of business including outsourced design services, research collaborations and a government focused vertical.

Currently, Mike is part of a team working for the US Department of Commerce that will play a key role to implement the CHIPS and Science Act’s historic investments in the semiconductor industry. He joined us in March for an overview of how the government is managing funding for manufacturing and R&D.

Mike returns to provide an update on progress and plans since his last Semiconductor Insiders podcast. He reviews details of funding work with organizations both large and small. The focus of the funding and results are discussed.

Mike also provides details about the work being done to address the talent shortage in the semiconductor industry, both from direct work with universities as well as collaboration with organizations across the ecosystem. Methods to reach across borders in the interest of a worldwide semiconductor ecosystem are also discussed.

Mike concludes with his views of what will be achieved in the coming months.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview: David Heard of Infinera

CEO Interview: David Heard of Infinera
by Daniel Nenni on 07-05-2024 at 6:00 am
Categories: CEO Interviews

DavidHeard

David Heard has served as CEO and has been a member of the Board of Directors since November 2020. Mr. Heard joined Infinera in June 2017 and served as our Chief Operating Officer from October 2018 to November 2020. During his time as COO, Mr. Heard was responsible for leading the innovation of new solutions and the overall operational excellence of the company, overseeing functions including corporate development, facilities, human resources, information technology, marketing, operations, product lifecycle management, quality, research and development and services.

Mr. Heard brings a proven track record of technology industry leadership, with more than 25 years of success in the industry. Prior to Infinera, Mr. Heard served as President of Network and Service Enablement at JDS Uniphase from 2010 to 2015, and as COO at BigBand Networks (now Arris) from 2007 to 2010. Earlier roles included President and Chief Executive Officer (CEO) at Somera (now Jabil), President and General Manager, Switching Division, at Tekelec (now Oracle), President and CEO at Santera Systems, and various positions at Lucent Technologies and AT&T.

Tell us about your company?
Infinera is a U.S.-based manufacturer of optical semiconductors and high-speed connectivity solutions for communications service providers, webscalers, and various industry verticals including government, energy, and healthcare. We build, sell, and deploy optical systems and subsystems that transport large amounts of data across fiber optic networks from shorter-reach metropolitan networks through ultra-long-haul and submarine networks. Our solutions provide the backbone for the internet, cloud services, and data center interconnect, and enable services such as 5G mobility, artificial intelligence, streaming video, and high-speed broadband. As part of delivering innovative, industry-leading solutions, Infinera owns and operates a U.S.-based compound semiconductor fab as well as an advanced testing and packaging facility.

What problems are you solving?
Bandwidth demands have been growing at more than 30% per year for more than 20 years. Infinera has been instrumental in helping network operators to cost-effectively keep up with the relentless growth in bandwidth. Leveraging our unique vertically integrated capabilities, Infinera has consistently provided innovative, flexible, and scalable solutions that increase capacity per fiber while driving down cost and power per bit.

What application areas are your strongest?
Infinera specializes in cost-effective scalable optical connectivity solutions. We focus on higher-capacity solutions capable of transmitting multiple terabits of data across all network applications, from intra-data center through ultra-long haul and submarine.

 What keeps your customers up at night?
Cost-effectively keeping up with their bandwidth demands, including rapidly growing demands between data centers driven by explosive applications such as artificial intelligence. Our customers also operate in highly competitive environments, driving the need to consistently provide differentiated service offerings.

What does the competitive landscape look like and how do you differentiate?
This is a growing field that is confronting the unprecedented operational challenges associated with the impact of AI workloads. There are traditional suppliers of optical networking gear focused on addressing this problem, as well as networking companies that can leverage a whole new ecosystem of optical pluggable technology. The environment remains extremely competitive, with the importance of vertical integration and performance leadership being critical to winning customers. Solutions providers need to consistently invest and innovate to bring new technologies and solutions to market that provide incremental benefits to network operators.

What new features/technology are you working on?
We continue to leverage our unique vertical integration capabilities, including our expertise in semiconductor material sciences, to bend the laws of physics to provide the Moore’s Law of economic scalability to critical network infrastructure. Our solutions and technologies are enabled by our U.S.-based semiconductor fab and our advanced test and packaging facility. We are currently bringing to market solutions that enable transmission of 800 Gb/s in a power-efficient pluggable form factor, 1.2 Tb/s in a high-performance embedded solution, and 1.6 Tb/s in an ultra-low-power, short-reach intra-data center solution.

How do customers normally engage with your company?
Networking solutions are typically large and complex deployments. As a result, we work closely with our customers to choose the right technology, optimize network designs, and deploy networks.

Our website is https://www.infinera.com/. We can be reached through our contact page: https://www.infinera.com/contact-us/. Our LinkedIn is https://www.linkedin.com/company/infinera/.

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CEO Interview: Dr. Matthew Putman of Nanotronics

CEO Interview: Dr. Matthew Putman of Nanotronics
by Daniel Nenni on 07-04-2024 at 6:00 am
Categories: CEO Interviews

MP1 T4A9487 smoothed V3 cropped

Dr. Matthew Putman is an American scientist, educator, musician, and film/stage producer. He is best known for his work in nanotechnology. Putman currently serves as the CEO of Nanotronics, an advanced machines and intelligence company that has redefined factory control through the invention of a platform that combines AI, automation, and sophisticated imaging to assist human ingenuity in detecting flaws in manufacturing. He recently built New York State’s first high-tech manufacturing hub, located in Building 20 of the Brooklyn Navy Yard.

Matthew has published over 30 papers and is an inventor on over 50 patent applications filed in the U.S. and other countries for his work on manufacturing, automation, inspection, instrumentation, super-resolution, and artificial intelligence. He is an expert in quantum computing and a founding member of The Quantum Industry Coalition. His groundbreaking inventions in manufacturing include the development of the world’s most advanced inspection instrument, which combines super-resolution, AI, and robotics.

Tell us about your company?
We have been in business for 14 years with the purpose of utilizing the latest in computation, especially advanced AI, to bring efficiencies to fabs. It has been a great journey as technology, in general, has improved. We manufacture our own imaging and analysis equipment to provide insights on defectivity and flaws in processes. Now, we use generative AI itself in factories to optimize recipes on production equipment. What was feedback to users is now feedback to the equipment itself. This has led us to our most ambitious endeavor, which is to take these technologies, package them in a modular fab, and deliver them around the world. This is Cubefabs.

A Cubefab can be in full operation in one year from the time of groundbreaking to full production and is a fraction of the price and size of a traditional fab. This has many advantages, and we are seeing interest from the semiconductor industry, as well as from countries and industrial groups that have not been able to enter the semiconductor market. Most importantly, I believe the first products that will come from a Cubefab are power devices that provide greater energy efficiency than anything else available. For applications in data centers and electric vehicles, this helps accelerate two of the largest growing markets with the largest need for efficiencies that they can’t get elsewhere. Cubefabs are democratizing fabs, as well as having a model that allows for regional independence, avoiding geopolitical risk.

What problems are you solving
We are addressing challenges in factories? by improving yields and producing devices with better energy efficiency. We envision a world where we can make rapid progress in the generative AI revolution by using AI to actually build. This offers a new perspective on imaging supply chains and the ability to produce quickly with the most innovative materials.

In which application areas are you strongest?
In our inspection and process control business, we serve a broad spectrum of applications, spanning from traditional silicon fabs to genomics and biotechnology. Additionally, we drive the adoption of emerging technologies like Quantum computing and advanced materials such as graphene. With a primary focus on compound semiconductors, we leverage our extensive data repository to develop AI systems that empower Cubefabs to manufacture next-generation compound semiconductors.

What keeps your customers up at night?
Fabs are getting more expensive and complex, and this is a huge challenge as they look to expand. So we often start by doing everything we can to help them improve yields and eliminate waste. I also think that everyone is concerned about the resources involved with building new factories. This is what I see keeping them up at night, and it keeps up up at night trying to find new solutions for them.

What does the competitive landscape look like and how do you differentiate?
I do not obsess over competition and instead focus on invention. We think of factory control through the lens of a type of AI control that others have just not adopted yet. So our main competition is different philosophies for how things can be built, more than it is competitors themselves. For Cubefabs, no other company that I know of is doing anything like it.

What new features/technology are you working on?
We are always improving AI models. We are always looking to build more robustness into our own products with our own models. As we see with AI in general, things are moving fast. We want to move as fast as the consumer applications in the world with factory innovation. So, new types of production control are always being tested in our labs.

How do customers normally engage with your company?
For our imaging and factory control product we do validation testing for them in advance. We know that we need to prove ourselves before they take the risk of changing the paradigm that they are used to.  Our applications engineers are speaking with the customers, understanding the problems they are having and then demonstrating our capabilities. With Cubefabs we are engaging with companies themselves as well as municipalities and countries as they look to solve these large problems. We know that this is doing something different, so we engage through a lot of dialogue and testing to make sure that we are aligned with them.

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LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis

LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis
by Daniel Nenni on 07-03-2024 at 2:00 pm
Categories: EDA, Emulation, Events, Synopsys

The Role of Realistic Workloads and Massively Parallel Power Analysis

As the complexity of modern System-on-Chip (SoC) designs continues to rise, achieving energy efficiency measured as performance per watt has become a crucial design goal. With the increasing demand for powerful, multifunctional chips, balancing performance with power consumption has become essential. Realistic workloads and advanced power analysis methods are vital for modern SoC design to help engineers improve energy efficiency early in the development process.

Traditional power analysis methods use synthetic simulation vectors to estimate SoC power consumption. These vectors, designed to mimic potential workloads, often miss the dynamic and unpredictable nature of real-world scenarios, resulting in significant lack of accuracy of power analysis. Often, designs that appear efficient in simulations may consume more power in actual use, leading to inefficient optimization efforts.

To address these limitations, incorporating software-driven workloads during power analysis is essential. Such realistic workloads provide an accurate representation of real-life applications, capturing nuances of power consumption that synthetic vectors miss. By emulating actual operating conditions, engineers can identify genuine power consumption bugs and optimize designs for better energy efficiency.

Advanced power analysis methods, such as using an emulation environment coupled with passively parallel power analysis, enable continuous monitoring and analysis of power consumption across multiple scenarios. This approach captures detailed power consumption data for real system operation, identifying patterns and anomalies that indicate inefficiencies. Such methods offer a true assessment of SoC power consumption, ensuring optimization efforts are based on accurate and relevant information.

One key benefit of using realistic workloads and advanced power analysis methods is the ability to ‘shift-left’ in the design process. Shifting left allows designers to address potential issues and optimizing designs earlier in the development cycle, preventing costly redesigns and ensuring the final product meets energy efficiency goals.

As the demand for powerful and efficient SoCs grows, traditional power analysis methods are no longer sufficient. Realistic workloads and advanced power analysis techniques offer a more accurate and comprehensive assessment of power consumption, enabling effective optimization. By shifting left and addressing energy efficiency early in development, companies can create competitive products that meet market demands.

Join our upcoming webinar on July 16 to learn more about these innovative approaches and enhance your SoC design’s energy efficiency. Register now to stay ahead of the rapidly evolving field of SoC design.

New Webinar: Making it Real: How to Use Realistic Workload Scenarios to Enhance Energy Efficiency in SoC Designs

Tue, Jul 16, 2024 10:00 AM – 11:00 AM PDT

Abstract:
As complexity of modern SoC designs is continuing to increase, energy efficiency – or performance per watt – has emerged as one of the primary design goals. Traditional methods of power analysis use synthetic simulation vectors – which may not represent real use cases. This approach may result in under-estimating power consumption, failing to detect real wasted power conditions, and guiding optimization efforts in the wrong direction. In this webinar, you will learn how using realistic workloads in the emulation environment, coupled with a passively parallel power analysis capability, provides a true assessment of the SoC power consumption, and enables you to have confidence to ‘shift-left’ to improve the energy efficiency of your design.

Speaker Bio:
William Ruby is the senior director of product management for Synopsys Power Analysis products. He has extensive experience in the area of low-power IC design and design methodology and has held senior engineering and product marketing positions with Cadence, ANSYS, Intel, and Siemens. William holds MBA, MSEE, and physics degrees, and has been awarded a patent in high-speed cache memory design.

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Solido Siemens and the University of Saskatchewan

Solido Siemens and the University of Saskatchewan
by Daniel Nenni on 07-03-2024 at 10:00 am
Categories: EDA, Siemens EDA

Solido USask 2024

A new tenured professor chair in the USask College of Engineering has been created to develop local talent and research, thanks to a significant gift from Siemens. (Photo: David Stobbe/University of Saskatchewan)

In my 40 years, I have worked for dozens of companies and just about everyone of them was acquired. Some of the acquisitions were accretive and some were not. Probably the best and most accretive one would be the Solido acquisition by Siemens EDA in 2017. I worked for Solido for ten years reporting to CEO Amit Gupta. I handled Taiwan and the foundry relationships, the most successful one being with TSMC of course. TSMC really put Solido on the map as both a customer and a great partner.

I have worked with companies all over the world but Solido was the first one based in Canada. It was also one of the best experiences of my career. I don’t think I have ever worked with a smarter group of people who were also fun to be associated with. Seriously, we had a LOT of fun traveling the world improving the quality of semiconductors and easing the design process.

Solido was founded in 2005 by Amit Gupta, who graduated from USask in 1999 with degrees in both EE and CS. Amit is now vice-president and general manager of Custom IC Verification at Siemens EDA and leads Solido’s products within the company. Berkely Design Automation and Fractal Technologies are also part of Amit’s domain, I worked for both BDA and Fractal as well. Siemens has the most aggressive acquisition group I have ever worked with but that is another story.

Siemens gift helps USask develop local talent in electronic chip design

The University of Saskatchewan (USask) has received a significant gift from Siemens to create a tenured professor chair in the USask College of Engineering for research and teaching that develops local talent in the large, fast-growing industry of electronic design automation (EDA).

“I am excited that Siemens is giving this gift to USask for the creation of the Siemens EDA Chair,” said Gupta. “The chair will advance EDA research and expertise of undergraduate and graduate students at USask that is critical in building the next generation of electronic devices. This will have a major impact on Saskatchewan’s technology sector.”

I chatted with Amit about this announcement and was not surprised to find out that Solido has aggressively recruited from USask. I remember when the acquisition happened, Solido had 50 employees in Saskatoon with the vast majority of them coming from USask. Today there are hundreds of employees in Saskatoon and more than 70% are from USask. By the way, Solido was one of the first companies to employ ML inside an EDA tool, another story as well.

The other part of this story is finding a Siemens EDA Chair. Applications are being accepted today!

Faculty, Siemens EDA Chair in Electronic Design Automation
Applications are invited from qualified individuals for a tenured or tenure-track faculty position in the Department of Electrical and Computer Engineering. The successful candidate will be appointed as the Siemens EDA Chair in Electronic Design Automation. The chairholder is expected to develop and teach courses in EDA at the graduate and undergraduate levels, establish a research program at the forefront of EDA development and compete successfully for external funding, engage with local industry working in the field, supervise student research, and undertake relevant administrative activities.

The University of Saskatchewan’s main campus is situated on Treaty 6 Territory and the Homeland of the Métis. The University of Saskatchewan is located in Saskatoon, Saskatchewan, a city with a diverse and thriving economic base, a vibrant arts community and a full range of leisure opportunities. The University has a reputation for excellence in teaching, research and scholarly activities and offers a full range of undergraduate, graduate, and professional programs to a student population of over 25,000.

The successful candidate must hold an earned Ph.D. in electrical or computer engineering or a closely related field and be eligible for registration as a professional engineer in Saskatchewan. We are seeking candidates who have demonstrated expertise in electronic design automation preferably in one or more of analog/mixed-signal verification, functional verification, verification methodologies for advanced process technologies, analog circuit simulation, statistical verification, custom verification, library characterization, or application of artificial intelligence techniques to EDA.  A publication record demonstrating research excellence and potential for establishing an independent research program is required.  Industrial experience in the design and application of EDA for custom IC verification is an advantage.  We are looking for a person with excellent communication and teaching skills and a demonstrated ability to work effectively in informal and formal groups with people from diverse communities, cultures and perspectives.  Depending on qualifications, appointment can be at the associate professor rank with tenure or at the tenure-track assistant professor rank.  Appointment with tenure requires a publication and teaching record that meets our standards for tenure.

Salary bands for this position for the 2024-2025 academic year are as follows:

Assistant Professor: $99,945 to $120,099; Associate Professor: $120,099 to $140,253

This position includes a comprehensive benefits package which includes a dental, health and extended vision care plan; pension plan, life insurance (compulsory and voluntary), academic long-term disability, sick leave, travel insurance, death benefits, an employee assistance program, a professional expense allowance, and a flexible health and wellness spending program.

Interested candidates must complete the applicant survey (link) and submit, via email, a cover letter; detailed curriculum vitae; a research plan outlining specific interests in EDA, a statement of teaching focus and philosophy including potential courses to be taught, a diversity statement explaining how you will contribute to equity, diversity and inclusion and the names and contact information of three professional references to:

Robert Johanson, Department Head
57 Campus Drive
University of Saskatchewan
Saskatoon, SK S7N 4L3
Email:  engrfaculty.recruitment@usask.ca

Status: Tenure Track
Employment Group: USFA
Full Time Equivalent (FTE): 1.0
Posted Date: 6/27/2024
Closing Date: Until Filled

Due to federal immigration requirements, we also ask candidates to indicate whether they are Canadian citizens, permanent residents, or are otherwise already authorized to work at this position for the duration of the appointment, with an explanation if this last category is indicated.

Review of applications will be ongoing however, applications will be accepted and evaluated until the position is filled. The anticipated start date is September 1, 2024.

Also Read:

Three New Circuit Simulators from Siemens EDA

Siemens Provides a Complete 3D IC Solution with Innovator3D IC

New EDA Tool for 3D Thermal Analysis

Podcast EP233: A Review of the Q1 2024 ESD Alliance Quarterly Electronic Design Market Data Report with Wally Rhines

Podcast EP233: A Review of the Q1 2024 ESD Alliance Quarterly Electronic Design Market Data Report with Wally Rhines
by Daniel Nenni on 07-03-2024 at 8:00 am

Dan is joined by Dr. Walden Rhines. Wally is a lot of things, CEO of Cornami, board member, advisor to many and friend to all. In this session, he is the Executive Sponsor of the SEMI Electronic Design Market Data Report.

Wally discusses the recent Q1 2024 ESD Alliance Quarterly Electronic Design Market Data Report with Dan. It was another strong quarter with 14.4% overall growth, an increase from the Q4 2023 number. Wally begins by saying, “the hits just keep coming.”

Overall growth was double digit for all but one region and all but one product category. Wally discusses these dynamics with Dan. It turns out there appears to be one region that is poised for a major comeback as well. The dynamics of the market in China are also discussed, along with a review of the work going on at Wally’s company, Cornami and the impact packaging innovation is having on the overall market.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Insights into Automotive AI in China

Insights into Automotive AI in China
by Bernard Murphy on 07-03-2024 at 6:00 am
Categories: AI, Automotive, China

Automotive AI in China min

Now that claims and counter claims about advances in foundational AI seem to be dying down, it becomes more interesting to look at the next wave – AI applications in key markets. Figuring out what is really happening here presents its own problems. Marketing and analyst literature still projects unbounded promise (now dialed back a bit), though some surveys suggest that enterprise adoption for business applications is still aspirational rather than mainstream. I now choose to look only at reasonably independent application surveys (here automotive), for example as reported in journals of peer reviewed literature.

Why a China focus?

The Chinese auto industry is the largest in the world by a wide margin as measured by unit production, which by itself is a pretty interesting statistic. That fact might be significant only within China if it weren’t for the fact their auto sales are also starting to grow in southeast Asia. While currently accounting for less that 10% of unit sales, Chinese OEMs are investing in factories across that region, expanding also in Brazil and now talking about Mexico. Separately, Volvo, now owned by a Chinese holding group, are promoting their EX30 and Polestar cars in Europe and the US. Whether or not these cars will clear US regulatory hurdles, it looks like Chinese automakers see opportunity to expand outside Asia.

The more important indicator for my purpose is that Chinese research in ADAS and autonomy is accelerating rapidly, no doubt motivated by tariffs/embargos. This is particularly obvious in automotive AI as judged by this paper from the China Automotive Technology and Research Center in Tianjin. Which in my view makes this area very interesting to watch.

Active production and R&D

Augmented reality (AR) heads-up displays (HUD) are one application space that seems to be tracking closely with Western R&D. There are several players here. Full-featured solutions depend on collaboration between the driver monitoring system (DMS)/pupil tracking, forward looking cameras, landscape perception (segmenting road regions, identifying nearby cars, pedestrians) and AR image rendering.

Subsets of this space are driver monitoring systems and occupant monitoring systems (OMS). Here DMS checks for closed or closing eyes or abnormal pose (is the driver slumped over or to one side?) to detect fatigue. OMS checks that you didn’t leave a child, an elderly person or a pet in the car. Here also there are multiple active deployments. Research here is looking at ensemble (multiple coupled) learning systems.

ADAS is already routine in China and BYD is actively testing L3 ADAS in Shenzen. This program started quite recently, so presumably will take time to build an adequate training database. Then again, the Chinese seem somewhat resigned to external monitoring so may be more open to external methods to assist car-based AI. Research here also is working with coupled systems including reinforcement learning, to predict vehicle trajectory and for lane keeping.

Fingerprint and facial recognition are already available to unlock and start some models, despite the occasional PR disaster. Research continues for handling challenging illumination conditions which can reduce accuracy for face-based recognition. Here again research is considering ensemble-based systems, presumably to recognize more complex facial characteristics than can be captured in a single training set. also factoring in physiological sensing for the driver. This is an intriguing video review of the new Xpeng G3 model, mentioning among other things facial recognition and physiological monitoring.

In cockpit control, hand gesture recognition as an alternate method of control is already available in some Chinese cars. Tencent has announced a mobility solution (I think voice-based) built on LLMs. While there has been an explosion in options in this space, I would imagine that will settle fairly quickly to a few survivors such as TenCent.

To round out in-cabin automation, 360o view monitoring and blind spot detection are now commonplace and advancing, for example looking for parking line markers and low obstacles (child, dog, kids bike).

Recognized challenges

The paper lists several challenges in execution and in adoption. Some of these are routine, others are interesting either for a different insight or for China-unique perspectives. There is recognition that on-board AI may not be sufficient for complex tasks and will need external (cloud) support. Which raises concerns about privacy and security. Chinese car buyers worry about this too according to the paper.

The authors also call out general low enthusiasm for AI-based features among Chinese drivers. They attribute this partly to learning curve but also partly to unpredictable quality in these systems. I think the argument here is that AI may be a great sales tool in the showroom but may see low usage in practice.

One problem they call out is weak linkage between hardware and software development teams, where they say in China collaborative hardware/software development still lags other countries.

Finally, the Chinese are wrestling with policy and regulatory concerns, just as we are. Even in that country there are no easy ways to bound factors like liability, privacy and security.

Takeaways

It seems clear in current deployment alone that Chinese auto makers are keeping up with other automakers, in the West and elsewhere in Asia. Meanwhile research also seems to be tracking research outside China. Whether we will see any of these cars in the US is now more a political question than a technical question, especially given the very low price tags on offer. I’m sure there will be quality problems, though our own automakers are hardly blameless in that department.

Worth continuing to watch.