At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:
In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that… Read More
Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More
Hyperscale data centers are evolving rapidly to meet the demands of high-bandwidth, low-latency applications, ranging from AI and high-performance computing (HPC) to telecommunications and 4K video streaming. The increasing need for faster data transfer rates has prompted a scaling of Ethernet from 51Tb/s to 100Tb/s. Numerous… Read More
Synopsys Webinar: Tuesday, November 28, 2023 | 10-11 am. PT
System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic
Increased vehicle connectivity options are vital to providing the best driving experience for consumers. However, the adoption of over-the-air software updates, numerous connectivity protocols (including Bluetooth, WiFi, 5G cellular, USB), and in-car networks like CAN, MIPI, and automotive Ethernet, accelerates cybersecurity… Read More
Join industry experts from aerospace, government, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI), highlighting some of the technological, manufacturing, and economic complexities as well as security, reliability, and safety challenges. The panelists will also share … Read More
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints
Nov 10 – Korea (Seoul)
Nov 14 – Taiwan (Hsinchu)
Nov 16 – Japan (Tokyo)
Join our TCAD Seminar to learn about the application of Synopsys TCAD solutions to accelerate the research, development, and optimization of semiconductor technologies. The seminar tracks cover all major semiconductor… Read More
NXP Tech Days Detroit provides automotive engineers with two days of intensive training, aimed at advancing skills and gaining familiarity with NXP’s roadmap of ground-breaking products and solutions.
Explore the potential of NXP products and solutions. We look forward to seeing you in person to share knowledge
