1.2 Terabit/s C2C Interface? Only with Interlaken!

If you are familiar with high bandwidth networking applications, you probably know this chip-to-chip (C2C) interface protocol. Interlaken architecture, fully flexible, configurable and scalable, is also an elegant answer to the need for very high bandwidth C2C communication. Interlaken is elegant because the protocol defines the controller specification and can interface with various SerDes architectures, up to 56 Gbps SerDes rates with Forward Error Correction (FEC).

The Interlaken protocol has clearly been defined to provide the lowest latency when interfacing two chips at very high speed. The definition is simple, allowing the best possible efficiency. If you compare Interlaken specification with PCI Express or Ethernet for example, it’s much, much simpler, making the protocol easy to implement albeit extremely powerful to connect devices together.

Interlaken is targeting high bandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories or data center applications. In any of these application, the chip will integrate complexes protocols based on high speed serial links supported by SerDes. Developing or buying a 56 Gbps or even a 28 Gbps is either a resource intensive task or an expansive solution. Because Interlaken has been defined to cope with any kind of SerDes, the chip maker can reuse internally the investment made one time to implement the more complex protocol.

Open-Silicon, a founding member of the Interlaken Alliance formed in 2007, is launching the 8[SUP]th[/SUP] generation of Interlaken IP core, this supporting up to 1.2 Tbps bandwidth. This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable.

The flexibility of the Interlaken IP core is translating into the multiple aggregate BW interfaces. As an example, a single Interlaken IP instance can be configured in-system to support different Interlaken interfaces: 1×1.2Tbps, 2x600Gbps or 4x300Gbps. On-chip implementation can be based on up to 48 SerDes lanes, when you use a 28 Gbps SerDes, or you can implement a 24 lanes solution when using a 56 Gbps solution.

The core is also highly configurable and scalable, illustrated by this features list:

–Support for 256 logical channels

–8-bit channel extension for up to 64K channels

–Independent SerDes lane enable/disable

–Support for SerDes speeds from 3.125Gbps to 56 Gbps

–Configurable number of lanes from 1 to 48

–Flexible user interface options:- 128b: 1x128b, 2x128b, 4x128b, or 8x128b
– 256b: 1x256b, 2x256b, 4×256, or 8x256b

–Programmable BURSTMAX from 64 bytes – 512 bytes

–Programmable BURSTMIN from 32 bytes – 256 bytes

–Simultaneous In-band and Out-of-Band flow control

–Programmable calendar

–Built-in error detection and interrupt structures

–Configurable error injection mechanisms for testability

According with Michael Howard, senior research director and advisor, carrier networks at IHS Markit, “with the unstoppable growth of high-bandwidth networking applications together with the desire to further technological advancements on a much quicker cadence, the demand for industry consortium standards that ensure interoperability grows sharply. It is for these reasons that solutions such as this chip-to-chip Interlaken IP core, will likely have high adoption into next generation routers and switches, packet processors, and high-end networking and data processing applications.”

“The demand for performance and bandwidth for applications in networking is growing exponentially,” said Vasan Karighattam, Vice President of Engineering for Open-Silicon. “With nearly a decade of experience building the Interlaken core, Open-Silicon has continued to provide its customers with leading-edge custom silicon and IP solutions that power next generation networking products. Open-Silicon remains committed to the Interlaken protocol and providing the highest-performance, most scalable Interlaken IP.”

The success of chip-to-chip Interlaken IP core adoption is based on the exponential growth of the bandwidth demand, with a 25% CAGR for 2015-2020 and a volume of 80 Exabytes per month in 2017, and the high interoperability level offered by the protocol. Moreover, the Interlaken IP core can be implemented in a SoC faster than any similar protocol, because it’s simpler and SerDes agnostic, allowing the chip maker to deliver a cost optimized SoC with a better time-to-market.

Open-Silicon’s 8th generation Interlaken IP is available today. For more information, please visit:
www.open-silicon.com/open-silicon-ips/interlaken-controller-ip/
or the Interlaken Alliance web site.

By Eric Esteve from IPnest

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