IEDM 2018 Imec on Interconnect Metals Beyond Copper

IEDM 2018 Imec on Interconnect Metals Beyond Copper
by Scotten Jones on 12-28-2018 at 7:00 am

At IEDM this December Imec presented “Interconnect metals beyond copper – reliability challenges and opportunities”. In addition to seeing the paper presented I had a chance to interview one of the authors, Kristof Croes. Replacements for copper are a hot subject and I will summarize the challenges and Imec’s work.


Since the early day of the semiconductor industry we have seen a steady progression in interconnect to finer lines, more layers and new metals. The electrical current in interconnect lines haven’t scaled down as fast as the lines cross sectional area and therefore the current density in the lines has steadily increased. Early interconnect was wide aluminum (Al) lines that eventually gave way to narrower aluminum-copper (AlCu) alloys and eventually copper (Cu). Today we are starting to see the move from Cu to alternate materials for the narrowest lines.

Interconnect for advanced logic is made of an interconnect hierarchy:


  • Local – at the lowest layers is the local interconnect between adjacent cells.
  • Intermediate – the intermediate level connects cells, modules and cores.
  • Global – the global interconnect provides clock and power.

    The characteristics of the three levels is summarized in figure 1.


    Figure 1. Interconnect Types.

    The narrowest lines occur at the local level and that will be the focus of this article.

    Interconnect Requirements
    Interconnect must meet a variety of requirements:


  • Resistance – the resistance of an interconnect line is determined by the line length, cross sectional area and resistivity of the material. The interconnect line resistance is shown in figure 2.


    Figure 2. Interconnect Line Resistance.

    From the table in the figure we can see that Cu has the lowest bulk resistivity of materials shown. However, the resistivity values shown her are the bulk resistivity values. At very small cross-sectional area of an interconnect line, electron scattering increases the material resistivity. The electron mean free path also included in the table is useful for estimating the increases in resistivity for small cross sectional area line. As can be seen from the table Cu has the longest mean electron mean free path of the material shown and therefore see the largest resistance increase at small cross-sectional area. When thinking about resistivity a figure of merit has emerged that is the resistivity multiplied by the electron mean free path.


  • Electromigration – electrons moving through an interconnect line transfer momentum to the interconnect material atoms. At high current densities and temperatures, the momentum transfer can cause migration of the atoms that make up the interconnect lines leading to voids and breaks in the line. Figure 3 presents a formula for estimating electromigration resistance.

    Figure 3. Electromigration Reliability.

    You can see from the table that there is a wide range of activation energies for materials. Al, the material used for interconnect early in the industry development has a low activation energy and therefore tends to have poor electromigration resistance. As mentioned previously the addition of Cu to Al, AlCu can improve the electromigration resistance (still used today for larger linewidth technologies). Figure 4 Illustrates AlCu.


    Figure 4. Aluminum-Copper.

    For pure materials the electromigration resistance can be estimated from the materials melting point and melting point is another material figure of merit.


  • Adhesion to, and migration through dielectric layers – when Al was the interconnect of choice it could be deposited right on the dielectric layers and it adhered well and didn’t migrate through the underlying films. With the switch to Cu, adhesion and migration became challenges. The standard practice with Cu is to use a tantalum-nitride (TaN) barrier film to prevent the Cu from migrating through the dielectric films and contaminating the underlying devices. The problem with barrier layers like this is that the barrier material has high resistivity and in order to have the needed barrier properties a minimum thickness is required. As interconnect linewidths shrink to smaller and smaller cross-sectional area the barrier layers become a larger percentage of the cross-sectional area and drive up resistance. The barrier resistance is a particular problem in the bottom of vias where the film is relatively thick compared to the area of the via. An ideal interconnect material would adhere well to the dielectric films and not require a barrier.
  • Patterning – in order to use a material for interconnect it must be patterned. With aluminum in the early days of the industry a simple wet etch was used with a photoresist pattern. As the linewidths shrunk the linewidths became more and more like the film thickness and an anisotropic etch solution was needed ushering in dry etching. Cu is difficult to dry etch and a switch to a damascene process was required. In a damascene process a trench is etched in the dielectric film, the trench is filled with Cu and then chemical mechanical planarization is used to remove any Cu above the trench opening. Any new material will need to be patterned by dry etch or a damascene process with CMP.
  • Stress – any interconnect material can’t be highly stressed.

    Imec work
    First, Imec is working to understand the limits of Cu and extend it as far as possible. The limits of Cu are:

    • Resistivity increases with shrinking line width – below 20nm exponential increase in line resistance.
    • Via resistance also goes up strongly due to the liner.
    • Thinners lines see more contribution of grains – around 10nm line can’t meet electromigration – smaller lines more grains from electroplating .

    Imec began their work on alternative materials by screening based on the two metrics we discussed previously – resistivity multiplied by electron mean free path and melting point. Figure 5 summarizes the properties for materials of interest.


    Figure 5. Imec alternative material screening.

    From figure 5 there are a lot of candidate materials that are potentially better than Cu based on the two figures of merit.

    Imec went on to integrate four of the more promising materials into actual interconnect structures and measured resistivity versus cross sectional area. The four materials were picked because they can be reasonably integrated. Figure 6, presents the Imec results.


    Figure 6. Imec integrated resistivity results.

    Rhodium and Iridium show the best results but Ruthenium (Ru) and Cobalt (Co) are similar and further along in the development process.

    Metal deposition options for these materials include atomic layer deposition (ALD), chemical vapor deposition (CVD) and electroplating.

    The main focus of this work was to evaluate Co and Ru reliability. The key findings to-date are:

    • Chip package interaction – 20% higher Co stress and 10% higher Ru stress versus Cu, don’t think it is very significant
    • TDDB – mobility of metal in dielectric -clean enough Ru does not go into dielectric – need to ionize the Ru for migration and clean Ru doesn’t, Ru doesn’t need barrier. Does need an adhesion layer (~1nm per AMAT later in session).
    • Eletromigration – standard test relies on flux divergence point, doesn’t exist without barrier at via bottom so you need to create one. Need high currents (over stressing) >80MA/cm2 – 1st order lifetime, still evaluating. They do see voids so grains are likely important. Need to understand it. They do see more Joule heating than Cu. Measure R vs T and . May be more of a reliability issue than electromigration, may limit allowable current, but need more data.

    Ru can be deposited with ALD or CVD, not aware of an electroplating process for Ru, Co can be electroplated (authors note: Intel and TSMC are both believed to be using Co electroplating).

    Patterning of Co is done with a CMP damascene process, it is hard to dry etch, Ru can be dry etched but to-date is difficult to CMP.

    Co requires a thin adhesion layer but does not need a barrier. Ru also doesn’t need a barrier layer and may not need an adhesion layer. Adhesion layers are better than barrier layers because they can be thinner and don’t even have to be continuous.

    The reliability work is still ongoing but to-date Co and Ru both look better than copper.

    Industry experience
    Alternate materials have multiple potential usages in interconnect stacks:

    • Caps – capping a Cu interconnect line with Co increases the electromigration resistance of the line. TSMC has been doing this since 16nm.
    • Barrier/seed – when Cu is plated a seed layer is required to plate onto. When Cu was first introduced a TaN barrier with a Cu seed were deposited by physical vapor deposition (PVD). Co (TSMC) and even Ru (Intel) seed layers are being introduced because copper wets better to these films improving fill. Ru seed layers also produce lower resistance plated copper.
    • Contacts – Co filled contacts have been introduced at 10nm (similar to foundry 7nm) by Intel and 7nm by TSMC. We don’t yet know for sure whether Samsung has Co filled contacts at 7nm but my expectation is they will.
    • Interconnect – Intel has introduced Co interconnects for metals 0 and 1 at 10nm. The resistance of the lines is higher than it would be for Cu but the lines are short and the via resistance is lower and electromigration is better. Imec has previously stated to me that around 36nm pitch is where Co may begin to offer a benefit and that Intel’s minimum metal pitch. You can see that write up here.

    Figure 7 summarizes the usage of Co and Ru in actual processes.


    Figure 7. Co and Ru in production processes.

    We are beginning to see cobalt integrated into production processes and even some ruthenium. The Imec work shown at IEDM to-date shows both materials will likely be superior to copper for reliability. As linewidths continue to shrink, we expect to see increasing use of Co and Ru.

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