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TechInsights
Posted on by Scotten Jones

IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium

IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium
by Scotten Jones on 07-21-2016 at 12:00 pm
Categories: Events, Foundries, TechInsights

At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview with someone from IMEC who worked on the technology. This last week I got a chance to speak with Dan Mocuta of IMEC about the work.

The first question you may ask is why Horizontal Nanowire (HNW) technology is interesting. In my previous blog on An Steegen’s “Secrets of Semiconductor Scaling” presentation I discussed the looming limits on FinFETs. Basically FinFET scaling is expected to end at the 7nm node (real node, 5nm node at the foundries). To continue to scale some type of new device structure is needed. HNW processing is very similar to a FinFET process and they provide improved electrostatics and scaling. Many researchers and leading technologists believe HNW will be the successor to FinFEts.

You can read my blog about An Steegen’s paper HERE.

In the IMEC work they created 2 – 8nm diameter horizontal silicon nanowires stacked on top of each other. The pitches are slightly relaxed from what is needed for a 7nm node in order to demonstrate the devices.

The process to fabricate the nanowires is as follows:
[LIST=1]

  • Ground plane implant – this is used to dope the surface of the wafer and suppress leakage due to parasitic transistors – this step is also typically seen in bulk FinFET processes.
  • Deposit a stack of Si/SiGe/Si/SiGe (Si = silicon, SiGe = silicon germanium) using an epitaxial reactor. This step is unique to HNW fabrication.
  • Fin formation – mask and etch to create “fins” and shallow trench isolation trenches. Refill the trenches with oxide and etch back the oxide to expose the “fins” – this is very similar to FinFET processing except the temperature for the fill needs to be lower for HNW and you are etching a Si/SiGe stack instead of just Si.
  • Dummy gate formation – deposit polysilicon, planarize and pattern it – same as FinFET fabrication.
  • Extension implants and spacer formation – same as FinFET fabrication.
  • Raised silicon source/drain – selective epitaxial growth of a raised silicon source/drain to make contact to the nanowire – for a typical FinFET process there would be Si raised source/drains for NMOS and SiGe raised source/drains for PMOS (more on this later).
  • HDD implants – ion implants into the raised source/drains – same as FinFET fabrication.
  • ILD0 – interlevel dielectric to cover the fins and planarization back to the tops of the dummy polysilicon gates – same as FinFET fabrication.
  • Dummy gate removal – etch out the polysilicon dummy gate – same as FinFET fabrication.
  • SiGe etch – a vapor phase HCl etch is used to etch out the SiGe in the “fin”, this releases the Si nanowires. This step is unique to HNW fabrication.
  • WF – the metal work functions are deposited and the gate area is filled – similar to FinFET fabrication.
  • Contact and Back End of Line – same as FinFET fabrication.

    There are of course a number of adjustments needed to accommodate HNW fabrication versus FinFET fabrication but with the exception of steps 2 and 10 the process is essentialy the same as a FinFET process.

    All of these details are available from the VLSI Technology paper. Looking at this flow I could see it was a single threshold voltage device and the lack of a raised SiGe source/drain for PMOS was a drawback. When I got to sit down with Dan Mocuda I asked him about the limitations in the work presented.

    Dan said it is a 7nm process but somewhat relaxed to focus on the device behavior as opposed to pushing the process. The current work is also single Vt but they have been successful at CMOS integration with dual work functions. With respect to raised SiGe source/drains for PMOS there are integration challenges because of the SiGe etch to release the Si nanowires but they are working on integrating it using spacers to protect the raised SiGe source/drain.

    The technology covered in this papers is also not a fully integrated process flow. For a full process you need ESD, I/O and multiple threshold voltages and they are working on all of that. I asked him if they might integrate FinFETs as part of the flow for I/O and he said there are ways to do that. You could selectively grow the Si/SiGe/Si/SiGe super lattice in one area and silicon in other areas to form FinFETs. This work was simplified version to demonstrate the technology and they are now working on smaller pitches and fully integrated process.

    We also discussed the limits of FinFET technology. Ultimately gate pitch limitations in FinFETs drives the need for nanowires. Fin widths can’t be less than 5nm because mobility collapses and gate length can’t be less than approximately 18nm for electrostatic control. Nanowires have better electrostatic control than FinFETs and can provide additional gate scaling leaving more space for contacts. They also have simulation studies that show lower variability for HNW than FinFETs so low voltage performance is better.

    One key area that still needs to be further evaluated for HNW is the vertical spacing between the wires. As the spacing between the wires gets smaller the process is simpler but if they get too close you lose electrostatic control.

    In terms of timing Dan believes HNW will be needed in the early 2020s as a true 5nm technology and he thinks it can be ready. It is built on FinFET replacement metal gate technology and if you get on the development train now you can be ready in 3 to 4 years! Many of the leading technologists I talk to also believe HNW is the 5nm solution!

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