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Samsung Keynote at IEDM

Samsung Keynote at IEDM
by Scotten Jones on 01-27-2022 at 6:00 am

Kinam Kim is a longtime Samsung technologist who has published many excellent articles over the years. He is now the Chairman of Samsung Electronics, and he gave a very interesting keynote address at IEDM.

He began with some general observations:

The world is experiencing a transformation powered by semiconductors that has been accelerated by COVID due to lock downs requiring contactless society. IT has become essential due to remote work, and remote education. Sensors, processors, and memory are all required. Digital adoption has taken a quantum leap and 25% remote work has increased to 58%. The digitization of the economy presents tremendous opportunity, smarts systems are generating tremendous amounts of data. Over the past 50 years, transistors per wafer are up by 10 million times, processor speeds by 100 thousand times, and costs down 47% per year. Semiconductors have similarity to the human brain, sensor are like eyes, processors and memory do the processing and storing. Smart phones combining sensors with processing enable new applications, sensors are taking on a bigger role with autonomous driving, AI, etc.

There was an interesting section on sensors but that isn’t really my area and I want to focus on the logic, DRAM and NAND roadmaps he presented.

Figure 1 presents the logic roadmap.

Samsung Keynote Figure 1

Figure 1. Logic Roadmap.

In figure 1 we can see how the contacted poly pitch (CPP) of logic processes has scaled over time. In the planar era we saw high-k metal gate (HKMG) introduced by Intel at 45nm and by the foundries at 28nm as well as innovations like embedded silicon germanium (eSiGe) to improve channel performance through strain. FinFETs were introduced by Intel at 22nm and adopted by the foundries at 14/16nm and have carried the industry forward for several nodes. Samsung is currently trying to lead the industry into the Gate All Around (GAA) era with horizontal nanosheets (HNS) they call multi bridge and HNS should carry the industry for at least two nodes. Beyond 2nm Samsung anticipates one of either a 3D Stacked FET (called a CFET or 3D FET by others), VFET as recently disclosed by IBM and Samsung, 2D materials or a negative capacitance FET (NCFET).

Figure 2 presents the roadmap for DRAM.

Samsung Keynote Figure 2

Figure 2 DRAM Roadmap

With EUV already ramping up in DRAM, the next challenges are shrinking the memory cell. Samsung is anticipating staking two layers of capacitors soon. A switch to vertical access transistor is anticipated in the later part of the decade followed by 3D DRAM. I haven’t been able to find much specific information on how 3D DRAM will be built but similar structures are illustrated in presentations from ASM, Applied Materials and Tokyo Electron as well as this presentation making it appear that the industry is converging on a solution.

Figure 3 presents the roadmap for NAND.

Samsung Keynote Figure 3

Figure 3 NAND Roadmap

Samsung’s latest 3D NAND is a 176-layer process that uses string stacking for the first time (first time string stacking for them, others have been string stacking for multiple generations) and peripheral under the array for the first time (once again the first time for them, others have been doing it for several generations). Next up is shrinking the spacing between the channel holes to improve density while also increasing the number of layers. Around 2025 Samsung is showing wafer bonding to separate the peripheral circuitry and memory array. At first, I was surprised by this, first off YMTC is already doing this and if Samsung thinks it offers an advantage, I am surprised they would wait so long to implement it. Secondly, I have cost modeled wafer bonding and I believe it is higher cost than the current monolithic approach. After thinking about it some more I am wondering if it is viewed as solving a stress problem that allows continued layer stacking and will be implemented when needed to continue stacking. Finally in the later part of the decade Samsung is anticipating material changes and further channel hole shrinks. The figure shown here doesn’t show it but, in their presentation, Samsung showed over a thousand layers for their 14th generation process.

In conclusion the keynote presents a view of continued scaling and improvement for logic, DRAM and NAND through the end of the decade.

Also read:

IBM at IEDM

Intel Discusses Scaling Innovations at IEDM

IEDM 2021 – Back to in Person

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