Webinar on Revolutionary Changes in SOC IP Access

Knowledge is power, and I’ve seen the trend over time of people getting more and deeper access to knowledge as each year goes by. I remember, as a student in high school back the in 70’s, the first time I wanted to buy stock in a company. You could only get a quote by calling a broker or visiting the broker’s office. Today you can get real time quotes on your computer – or phone even. The same goes for researching investments. Before, you needed to have personal connections or pay hefty research fees and commissions. Now you can use google to get everything you need, and then some.

This is just one example. We have seen the same trend in everything you can buy. However, one of the last areas to provide online research and the ability to purchase online is semiconductor IP. Granted this is a niche market, but access to this information is life or death for fabless semiconductor companies.

Looking at the changes in the semiconductor business, it is easy to see how access to each component of the chip design process has expanded. Before the fabless movement, only designers at companies that had a wafer fab could even consider getting access to chip design technology – tools and IP. Then came fabless, but a lot of key information about available IP was shrouded in secrecy. Or, in many cases there simply were no choices available – you took what you could get.

Right now, we are crossing a Rubicon in chip design. The equivalent of the Back to the Future self-tying shoes for IP selection is available to fabless chip designers. eSilicon has rolled out its STAR navigation platform that puts real live data on PPA into the designer’s hands, before money has been committed, contracts have been signed and hard decisions have been cast in stone.

Designers can go online with eSilicon’s STAR navigation system to get detailed information on many types of IP, including memory blocks. Because of the wide range of configurations and options, the correct selection of memory blocks can have a huge effect on every aspect of an SOC design.

To demystify the process and show the level of accessibility they provide, eSilicon is hosting a webinar that will walk designers through the complete process. The webinar will be on Wednesday October 26 at both 9AM and 9PM Pacific Daylight Time. They will cover examining PPA data for memory alternatives and exploring different architectures. With this system it is even possible to download front end models to verify the design choices. Lastly they will demonstrate how a quote is generated so you can purchase the IP online.

More blogs by Tom Simon