This week Cadence Design, Lumerical Solutions and PhoeniX Software hosted a two-day photonic summit and workshop. The first day had nearly 100 registered participants and featured industry leaders from Global Foundries, UCSB, MIT, Hewlett Packard Enterprise, General Electric, Boeing, Rockley Photonics, and Juniper Networks speaking about their current efforts with integrated photonics and the emerging photonics ecosystem. The second day of the summit was comprised of a full-day hands-on session where more than 70 participants were introduced to a new top-down, schematic-driven design, verification and implementation flow for electro-optical integrated circuits.
The new flow features Cadence’s extensive suite of custom, analog and mixed-signal design functionality combined with a new set of capabilities that promises to enable the co-design of systems comprised of electrical and optical components in one design automation environment. One of the things that stood out for me while watching the second-day session was that this wasn’t just another set of disparate tools that were being strung together to make a flow. Indeed, Cadence has thoughtfully made extensions to their design database and infrastructure to enable photonic design. The devil is in the details of course, but we learned that Cadence, PhoeniX and Lumerical have been working together for over two years now to get to this point. It was not an easy endeavor.
There is no way to describe everything that was discussed and shown in the all-day session in this short article, as evidenced by the fact that the participants all went home with an almost 200 page document describing the flow. None the less I will endeavor to give you the 50,000 foot birds eye view of what I saw. First and foremost the flow is an extension of Cadence’s front-to-back SDL (schematic driven layout) flow for custom, analog and mixed signal design. Everything you loved and hated about that flow is still there. Key additions to the flow for photonics included :
- new layer types in the technology file to enable connectivity checks,
- new pin types for optical connections
- new photonics-based schematic checks
- frequency and time-domain optical circuit simulation support in ADE ( via the Lumerical engines)
- configuration management of optical and electrical views for circuit simulation partitioning and netlisting
- a fully parameterized set of photonic building blocks that can be mapped onto different technology processes ( via the PhoeniX engines)
- the ability to create and characterize photonic modules including the creation of compact models (via PhoeniX layout engines + Lumerical FDTD, electrical and thermal solvers)
- full curvilinear shape generation including all angle rotations and phase-aware auto-waveguide routing ( via the PhoeniX engines)
- forward annotation of design parameters and constraints from the schematic to the layout through CDF including the use of parameterized pcells that interact with the PhoeniX curvilinear engines for module and waveguide creation
- real-time checking of schematic vs layout parameter mismatch
- back annotation of changes to parameters and physical modules and waveguide routing from from layout to schematic to simulation
- an extensive wrapping of PhoeniX and Lumerical commands in skill, enabling designers to use the full power of both Phoenix and Lumerical tools directly from within the Cadence environment
- beginnings of an electrical / optical co-simulation methodology and infrastructure including the use of characterized and parameterized photonic building blocks stored in foundry specific process design kits (PDK).
This set of capabilities is a huge step forward for integrated photonic designers and especially those companies who are struggling to integrate and co-design their electrical and photonic systems. The new flow also fills some significant gaps in Cadence’s previous capabilities for photonic design, namely curvilinear shape and all angle rotations along with photonic simulators and solvers. A couple of remaining areas still to be worked are a more efficient DRC process to reduce the amount of spurious false error reporting caused by all of the curvilinear shapes and more work on the integration and analysis of IC, PIC and packaging. More to come on these items at a later date.
It’s still early days for the flow but the fact that Cadence, PhoeniX and Lumerical were able to take more than 70 participants through a hands-on exercise of the flow in a single day was a testament in and of itself that the flow is already robust enough for the challenge. I was impressed and anyone that knows me, knows that means something. I’m not from Missouri, but I grew up right next door to it. Show me – and that they did.Share this post via: