Life Without EUV: SPIE Day 2

I previously published a summary of day 1 of SPIE and I wanted to follow up with observations from successive days.

SPIE, the international society for optics and photonics, was founded in 1955 to advance light-based technologies.Serving more than 256,000 constituents from approximately 155 countries, the not-for-profit society advances emerging technologies through interdisciplinary information exchange, continuing education, publications, patent precedent, and career and professional growth. SPIE annually organizes and sponsors approximately 25 major technical forums, exhibitions, and education programs in North America, Europe, Asia, and the South Pacific. www.spie.org
Tuesday 2/24 – day 2

Optical lithography with and without NGL for single-digit nanometer nodes – Burn Lin, TSMC
The paper began with a discussion of growth in cost per node from the 1.15x per node increase to 1.4x for the latest node. Issues with overlay were really the heart of this paper. The author discussed the many issues that can lead to poor overlay from warpage, back side particles, wafer non linearity due to uneven heating, mask flatness and particles, lens heating and others. The

The move to multi patterning is making overlay an even bigger issue. Overlying multi patterning over single patterning or multi patterning with 3 photo and etch steps on multi patterning with 2 photo and etch steps creates higher order overlay issues.

The authors sees ArFi single exposure limited to approximately an 80nm pitch. Multi pattering gains resolution by pitch splitting but creates cost and overlay issues. He see EUV with an NA > 0.33 as difficult and expensive to achieve as well as k1 < 0.4 being difficult yielding a pitch of 32.4nm, marginal for 7nm, may need some double patterning.

The key to solving the overlay issue according to the author is to go to single exposure and etch at all layers. A table was presented indicating that the least expensive option at N7 is single exposure with Multi beam E Beam (MEB). Interestingly this opinion appears to contrast with the more main stream TSMC approach of using EUV.

The author also discussed Directed Self Assembly (DSA) as a very useful option to reduce costs but one still having CD uniformity plus placement and defect issues.

Also read: EUV Makes Progress and Other Observations From SPIE 2015

Evolving optical lithography without EUV – Donis G. Flagello, Nikon
Nikon has stopped working on EUV leaving it to ASML. I came to this paper very interested to hear what Nikon’s roadmap is to move forward without EUV. I have to say this was one of the more disappointing papers I attended at SPIE. It was long on quirky “Latin like” nomenclatures but short on an actual roadmap.

Relative costs for 193i double and triple patterning versus EUV were presented showing EUV to be more expensive. Continued progress in ArFi scanner throughput was noted with additional increases in wafers per days forecast for 2018. Whereas 3,500 wpd was common in 2010, today 4,000 wpd is common and by 2018 6,000 wpd is forecast.

The author also offered that gains for 450mm are better for ArFi than for EUV.

There was a fair amount of discussion of resolution enhancement techniques that are being sued in optical microscopy and the potential to apply them to lithography. Immersion lithography after all is a lithography application of immersion techniques that have been used in microscopy for decades. This however struck me as a proposal for a research program as opposed to a particle roadmap.

Integration of NAND flash memory ISO multilayer etching to improve productivity – Chang-kwon Oh, SK Hynix
3D NAND is an area of intense interest for me and I am currently working on a blog discussing the impact I expect it to have on the industry.

Some of the key take aways from this paper were that for 2D NAND costs take off at the 1x, 1y and 1z generations. Cell to cell cross talk is also an increasing issue for 1x and subsequent generations.

SK Hynix expects to introduce 3D NAND in 2015.

3D NAND offers improved density, writing speed, endurance and power efficiency. The trade off is productivity, yield and complexity.