Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
by Daniel Nenni on 05-04-2023 at 6:00 am

Alphawave Semi 3nm Eye Diagram

There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node in the history of the TSMC FinFET family, absolutely.

(Graphic: TSMC)

In order to tape-out to 3nm you need IP and high speed SerDes IP is critical for HPC applications such as AI which is now the big semiconductor driver for leading edge silicon. Enabling chiplets at 3nm is also a big deal and that is the focus of this well worded announcement:

Successful launch of 3nm connectivity silicon brings chiplet-enabled custom silicon platforms to the forefront Alphawave Semi 3nm Eye Diagram

(Graphic: Business Wire)

LONDON, United Kingdom, and TORONTO, Canada – April 25, 2023 – Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity for the world’s technology infrastructure, today announced the bring-up of its first connectivity silicon platform on TSMC’s most advanced 3nm process with its ZeusCORE Extra-Long-Reach (XLR) 1-112Gbps NRZ/PAM4 serialiser-deserialiser (“SerDes”) IP.

An industry-first live demo of Alphawave Semi’s silicon platform with 112G Ethernet and PCIe 6.0 IP on TSMC 3nm process will be unveiled at the TSMC North America Symposium in Santa Clara, CA on April 26, 2023.

The 3nm process platform is crucial for the development of a new generation of advanced chips needed to cope with the exponential growth in AI generated data, and enables higher performance, enhanced memory and I/O bandwidth, and reduced power consumption. ZeusCORE XLR Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the Alphawave Semi product portfolio and on the 3nm process will pave the way for the development of future high performance AI systems. It is a highly configurable IP that supports all leading edge NRZ and PAM4 data center standards from 1112 Gbps, supporting diverse protocols such as PCIe Gen1 to Gen6 and 1G/10G/25G/50G/100 Gbps Ethernet.

This flexible and customizable connectivity IP solution together with Alphawave Semi’s chiplet-enabled custom silicon platform which includes IO, memory and compute chiplets, allows end-users to produce high performance silicon specifically tailored to their applications. Customers can benefit from Alphawave Semi’s application optimized IP-subsystems and advanced 2.5D/3D packaging expertise to integrate advanced interfaces such Compute Express Link (CXLTM), Universal Chiplet Interconnect ExpressTM (UCIeTM), High Bandwidth Memory (HBMx), and Low-Power Double Data Rate DRAM (LP/DDRx/) onto custom chips and chiplets.

“We are thrilled to be one of the first companies to successfully demonstrate our highest performance silicon platform with our XLR 112G Ethernet and PCIE6.0 SerDes IP on TSMC’s most advanced 3nm technology”, said Tony Pialis, CEO and co-founder of Alphawave Semi. “This represents a significant stepforward in our execution of Alphawave Semi’s strategy to be a vertically-integrated semiconductor leader in high-speed connectivity. Thanks to our rapidly growing partnership with TSMC through the Open Innovation Platform© (OIP), we continue to deliver innovative, high-performance custom silicon and IP solutions to our customers in data center, compute, networking, AI, 5G, autonomous vehicles, and storage applications.”

“Alphawave Semi continues to see growing demand from our hyperscaler customers for purpose-built silicon with very high-speed connectivity interfaces, fueled by an exponential increase in processing of AI-generated data”, said Mohit Gupta, SVP and GM, Custom Silicon and IP, Alphawave Semi. “We’re engaging our leading customers on chiplet-enabled 3nm custom silicon platforms which include IO, memory, and compute chiplets. Our Virtual Channel Aggregator (VCA) partnership with TSMC has provided invaluable support, and we look forward to accelerating our customers’ high-performance designs on TSMC’s 3nm process.”

About Alphawave Semi

Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

Alphawave Semi at the Chiplet Summit

Alphawave IP is now Alphawave Semi for a very good reason!

High-End Interconnect IP Forecast 2022 to 2026

 


TSMC 2023 North America Technology Symposium Overview Part 5

TSMC 2023 North America Technology Symposium Overview Part 5
by Daniel Nenni on 04-27-2023 at 10:00 am

Global Footprint

TSMC also covered manufacturing excellence. The TSMC “Trusted Foundry” tagline has many aspects to it, but manufacturing is a critical one. TSMC is the foundry capacity leader but there is a lot more to manufacturing as you will read here. Which brings us to the manufacturing accomplishments from the briefing:

To meet customers’ growing demand, TSMC has accelerated its fab expansion rate:
  • From 2017 to 2019, TSMC built around 2 phases of fabs on average per year.
  • From 2020 to 2023, the average will significantly increase to around 5
  • In the past two years, TSMC started the construction of 10 new phases in total, including 5 phases of wafer fabs in Taiwan, 2 phases of advanced packaging fabs in Taiwan, and 3 phases of wafer fabs overseas.
    • The overseas capacity of 28nm technology and below will be 3X larger in 2024 than it was in 2020.
    • In Taiwan, phases 5, 6, and 8 of Fab 18 in Tainan are the base of TSMC’s N3 volume production. In addition, TSMC is preparing new fabs, Fab 20 in Hsinchu and a new site in Taichung, for N2 production.
    • In the US, TSMC is planning for 2 fabs in Arizona.
  • The first fab for N4 has started tools move-in, and volume production will be in 2024.
  • The second fab is under construction now and is planned for N3 production.
  • Combined capacity for both fabs will reach 600K wafers per year.
    • In Japan, TSMC is building a fab in Kumamoto to provide foundry services for 16/12nm and 28nm family technologies to address strong global market demand for specialty technologies. Construction of this fab has begun and volume production will be in 2024.
    • In China, a new phase for 28nm technology started volume production in 2022.

TSMC’s leadership on advanced technology defect density (D0) and defective parts per million (DPPM) has demonstrated its manufacturing excellence.

    • The process complexity of N5 is much higher than N7, but N5’s yield improvement is even better than N7 at the same stage.
    • TSMC’s N3 technology has demonstrated industry-leading yield in high-volume production, and its D0 performance is already on par with N5 at the same stage.
      • TSMC’s N7 and N5 technologies have demonstrated industry-leading DPPM, including smartphones, computers, and cars, and TSMC is confident that N3 DPPM will catch up with N5 very soon.
3DFabric™ Manufacturing
  • By leveraging TSMC’s industry-leading 3DFabric™ manufacturing, customers can overcome the challenges of system-level design complexity and speed up product innovation.
  • CoWoS and InFO families have reached fairly high-level yields very soon after their volume productions.
  • The integrated yield of SoIC and advanced packaging will achieve the same level as the CoWoS and InFO families.
Green Manufacturing
    • To achieve the goal of net zero emissions by 2050, TSMC continues to evaluate and invest in all types of opportunities to reduce greenhouse gas emissions.
    • In 2022, TSMC’s direct greenhouse gas emissions have significantly dropped to 32% from 2010 levels.
    • This was achieved through reducing process gas consumption, replacing global warming potential gases, installing on-site abatement systems, and improving gas removal efficiency.

TSMC aims to double production energy efficiency for every process node after five years of volume production.

    • For N7 technology, the energy efficiency improved by 5X in the fifth year of its volume production.
    • For N5 technology, TSMC expects to see energy efficiency improvement by 5X by 2024.
    • TSMC has built an innovative chiller system with AI capabilities, which significantly contributed to improving cooling energy efficiency.

Last year, TSMC’s first water reclamation plant in southern Taiwan started supplying 5,000 metric tons of water per day. Today, it’s 20,000 tons per day.

    • By 2030, TSMC’s tap water consumption per unit of production will be reduced to 60% of 2020 level.
    • At TSMC Arizona, TSMC plans to build an industrial water reclamation plant to help the company reach near-zero liquid discharge. When completed, TSMC Arizona will be the greenest semiconductor manufacturing facility in the U.S.

After attending a handful of conferences in 2023 I must say that the TSMC Technical Symposium was by far the best. I don’t know the final attendance numbers but more than 1,600 people registered to attend this event. The exhibit hall was very busy and well stocked with food. Quite a few of the companies we work with on SemiWiki were exhibiting and I was told that for the cost it had by far the best ROI of semiconductor conferences.

The TSMC Technical Symposium will next go to Austin, Boston, Taiwan, Europe, Israel, China, and Japan. TSMC certainly knows how to build an ecosystem of customers, partners, and suppliers, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4


TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 4
by Daniel Nenni on 04-27-2023 at 8:00 am

TSMC Specialty Technology 2023

TSMC covered their specialty technologies in great detail. Specialty is what we inside the ecosystem used to call weird stuff meaning non-mainstream and fairly difficult to do on leading edge processes.  Specialty technologies will play an even more important part of semiconductor design with the advent of chiplets where die from specialty processes can be integrated with mainstream process die.

Specialty processes also fill fabs. As you can see TSMC is pushing heavily on N6RF to fill the N7 fabs. Here is the lengthy list of specialty accomplishments from the media kit:

TSMC offers the industry’s most comprehensive specialty technology portfolio, covering Power Management, RF, CMOS image sensing, and much more for a broad range of applications:

  • Automotive
    • As the automotive industry moves toward autonomous driving, compute requirement is increasing at a very fast rate and needs the most advanced logic technology. By 2030, TSMC expects that 90% of all cars will have ADAS function, with L1, L2, and L2+/L3 each taking up 30% of that market.
    • In the past three years, TSMC rolled out ADEP (Automotive Design Enablement Platform) by offering industry-leading Grade-1 qualified N7A and N5A to unleash customers’ automotive innovation.
    • To give customers a head start on automotive product design before technology is auto-ready, TSMC introduced Auto Early as a steppingstone to enable an early design start and shorten product time-to-market.
      • N4AE, based on N4P, enables customers to start risk production in 2024.
      • N3AE serves as a steppingstone to N3A, which will be fully automotive qualified in 2025.
      • N3A, once qualified and released, will be the world’s most advanced automotive logic technology.
  • Advanced RF Technologies for 5G & Connectivity
    • In 2021, TSMC released N6RF with best-in-class transistor performance, including speed and power efficiency, based on our record-setting 7nm logic technology.
    • Combining the superb RF performance and excellent 7nm logic speed and power efficiency, TSMC’s customers can enjoy 49% power reduction from an RF SoC chip with half digital and half analog thru migration from 16FFC to N6RF releasing the power budget of mobile devices to support other growing features.
    • Today, TSMC announced the most advanced RF CMOS technology, N4PRF, that will be released in the second half of 2023.
      • Offers 77X logic density increase and 45% logic power reduction under the same performance moving from N6RF.
      • 32% MOM cap density increase in N4PRF is offered when compared with its predecessor, N6RF.
  • Ultra-Low Power
    • TSMC’s ultra-low power solutions continue to drive Vdd reduction to push power saving, which is essential to electronics.
    • With continued technology enhancement to lower minimum Vdd from 0.9V at 55ULP to less than 0.4V in N6e, TSMC offers a wide range of voltage operation to enable dynamic voltage scaling design for optimal power/performance.
    • TSMC’s coming N6e solution can provide around 9X logic density with >70% power reduction vs. the N22 solution, an attractive solution for wearables.
  • MCU / Embedded Nonvolatile Memories
    • TSMC’s most advanced eNVM technology has progressed to 16/12nm FinFET-based technology, which allows customers to leverage superb performance in compute from FinFET transistors.
    • Due to the growing complexity of traditional floating gate-based eNVM or ESF3, TSMC has also heavily invested in new embedded memory technologies, such as RRAM and MRAM.
    • Both new technologies have now come to fruition, going into production at 22nm & 40nm nodes.
    • TSMC is planning for 6nm development
  • RAM: Moved into 40/28/22RRAM production during the first quarter of 2022
    • TSMC’s 28RRAM is also progressing well, with reliable performance that is automotive capable.
    • TSMC is now developing the next generation 12RRAM, which is expected to be ready by the first quarter of 2024.
  • MRAM: 22MRAM started production in 2020 for IoT applications. Now TSMC is working with customers to bring MRAM technology to future automotive applications and expects to qualify for automotive Grade 1 in the second quarter of 2023.
  • CMOS Image Sensing
    • While the smartphone camera has been the main driving force of CMOS image sensing technology, TSMC expects that automotive cameras will drive the next wave of CIS growth.
    • To serve the future sensor requirements and achieve even more high-quality and intelligent sensing, TSMC has been working on multi-wafer stack solution, demonstrating new sensor architectures such as stacked pixel sensors, the smallest footprint for global shutter sensors, event-based RGB fusion sensors, and AI sensors with integrated memory.
  •  Display
    • TSMC is focusing on higher resolution and lower power consumption for many new applications, driven by 5G, AI, and AR/VR.
    • The next generation high-end OLED panel will require more digital logic and SRAM content, and a faster frame rate. To address this need, TSMC is bringing its HV technology down to 28nm generation for better energy efficiency and higher SRAM density.
    • TSMC’s leading µDisplay on silicon technology can deliver up to 10X pixel density to achieve the higher resolution needed for near-eye displays like those used in AR and VR.

You can see more detailed descriptions of TSMC’s specialty offerings of MEMs Technology, CMOS Image Sensor, eFlash, MS/RF, Analog, HV, and BCD HERE.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 5


TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 3
by Daniel Nenni on 04-27-2023 at 6:00 am

3DFabric Technology Portfolio

TSMC’s 3DFabric initiative was a big focus at the symposium, as it should be. I remember when TSMC first went public with CoWos the semiconductor ecosystem, including yours truly, let out a collective sigh wondering why TSMC is venturing into the comparatively low margin world of packaging. Now we know why and it is  absolutely brilliant!

In 2012 TSMC introduced, together with Xilinx, the by far largest FPGA available at that time, comprised of four identical 28 nm FPGA slices, mounted side-by-side, on a silicon interposer. They also developed through-silicon-vias (TSVs), micro-bumps and re-distribution-layers (RDLs) to interconnect these building blocks. Based on its construction, TSMC named this IC packaging solution Chip-on-Wafer-on-Substrate (CoWoS).

This building blocks-based and EDA-supported packaging technology has become the de-facto industry standard for high-performance and high-power designs. Interposers, up to three stepper fields large, allow combining multiple die, die-stacks and passives, side by side, interconnected with sub-micron RDLs. Most common applications were combinations of a CPU/GPU/TPU with one or more high bandwidth memories (HBMs).

In 2017 TSMC announced the Integrated FanOut technology (InFO). It uses, instead of the silicon interposer in CoWoS, a polyamide film, reducing unit cost and package height, both important success criteria for mobile applications. TSMC has already shipped tens of millions of InFO designs for use in smartphones.

In 2019 TSMC introduced the System on Integrated Chip (SoIC) technology. Using front-end (wafer-fab) equipment, TSMC can align very accurately, then compression-bond designs with many narrowly pitched copper pads, to further minimize form-factor, interconnect capacitance and power.

Today TSMC has 3DFabric, a comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. Here are the TSMC related accomplishments from the briefing:

  • TSMC 3DFabric consists of a variety of advanced 3D Silicon Stacking and advanced packaging technologies to support a wide range of next-generation products:
    • On the 3D Si stacking portion, TSMC is adding a micro bump-based SoIC-P in the TSMC-SoIC® family to support more cost-sensitive applications.
    • The 2.5D CoWoS® platform enables the integration of advanced logic and high bandwidth memory for HPC applications, such as AI, machine learning, and data centers. InFO PoP and InFO-3D support mobile applications and InFO-2.5D supports HPC chiplet integration.
    • SoIC stacked chips can be integrated in InFO or CoWoS packages for ultimate system integration.
  • CoWoS Family
    • Aimed primarily for HPC applications that need to integrate advanced logic and HBM.
    • TSMC has supported more than 140 CoWoS products from more than 25
    • All CoWoS solutions are growing in interposer size so they can integrate more advanced silicon chips and HBM stacks to meet higher performance requirements.
    • TSMC is developing a CoWoS solution with up to 6X reticle-size (~5,000mm2) RDL interposer, capable of accommodating 12 stacks of HBM memory.
  • InFO Technology
    • For mobile applications, InFO PoP has been in volume production for high-end mobile since 2016 and can house larger and thicker SoC chips in smaller package form factor.
    • For HPC applications, the substrateless InFO_M supports up to 500 square mm chiplet integration for form factor-sensitive applications.
  • 3D Silicon stacking technologies
    • SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
    • SoIC-X is based on bumpless stacking and is aimed primarily at HPC applications. Its chip-on-wafer stacking schemes feature 4.5 to 9μm bond pitch and has been in volume production on TSMC’s N7 technology for HPC applications.
    • SoIC stacked chips can be further integrated into CoWoS, InFo, or conventional flip chip packaging for customers’ final products.
  • 3DFabric™ Alliance and 3Dblox Standard
    • At last year’s Open Innovation Platform®(OIP) Forum, TSMC announced the new3DFabric™ Alliance, the sixth OIP alliance after the IP, EDA, DCA, Cloud, and VCA alliances, to facilitate ecosystem collaboration for next-generation HPC and mobile designs by:
      • Offering 3Dblox Open Standard,
      • Enabling tight collaboration between memory and TSMC logic, and
      • Bringing Substrate and Testing Partners into Ecosystem.
    • TSMC introduced 3Dblox™ 1.5, the newest version of its open standard design language to lower the barriers to 3D IC design.
      • The TSMC 3Dblox is the industry’s first 3D IC design standard to speed up EDA automation and interoperability.
      • 3Dblox™ 1.5 adds automated bump synthesis, helping designers deal with the complexities of large dies with thousands of bumps and potentially reducing design times by months.
      • TSMC is working on 3Dblox 2.0 to enable system prototyping and design reuse, targeting the second half of this year.

Above is an example of how TSMC 3DFabric technologies can enable an HPC chip. It also supports my my opinion that one of the big values of the Xilinx acquisition by AMD was the Xilinx silicon team. No one knows more about implementing advanced TSMC packaging solutions than Xilinx, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

 


TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 2
by Daniel Nenni on 04-26-2023 at 8:00 pm

TSMC N3 Update 2023

The next topic I would like to cover is an update to the TSMC process node roadmap starting with N3. As predicted, N3 will be the most successful node in the TSMC FinFET family. The first version of N3 went into production at the end of last year (Apple) and will roll out with other customers in 2023. There is a reported record amount of N3x design starts in process and from what I have heard from the IP ecosystem, that will continue.

Not only is N3 easy to design to, the PPA and yield is exceeding expectations. While I’m hearing good things about N2 I still think the mainstream chip designers will stick to N3 for quite some time and the ecosystem agrees.

Meanwhile the competition is still working on 3nm. Intel 3 for foundry customers is still in process and Samsung 3nm was skipped by all. I still have not heard of a successful tape-out to Samsung 3nm from a customer name that I recognize.

Here are the TSMC N3 accomplishments from the briefing:

  • N3 is TSMC’s most advanced logic technology and entered volume production in the fourth quarter of 2022 as planned; N3E follows one year after N3 and has passed technology qualification and achieved the performance and yield targets.
  • Compared with N5, N3E offers 18% speed improvement at the same power, 32% power reduction at the same speed, a logic density of around 6X, and a chip density of around 1.3X.
  • N3E has received the first wave of customer product tape-outs and will start volume production in the second half of 2023.
  • Today, TSMC is introducing N3P and N3X to enhance technology values and offer additional performance and area benefits while preserving design rule compatibility with N3E to maximize IP reuse.
  • For the first 3 years since inception, the number of new tape-outs for N3 and N3E is 5 to 2X that of N5 over the same period, because of TSMC’s technology differentiation and readiness.
  • N3P: Offers additional performance and area benefits while preserving design rule compatibility with N3E to maximize IP reuse. N3P is scheduled to enter production in the second half of 2024, and customers will see 5% more speed at the same leakage, 5-10% power reduction at the same speed, and 1.04X more chip density compared with N3E.
  • N3X: Expertly tuned for HPC applications, N3X provides extra Fmax gain to boost overdrive performance at a modest trade-off with leakage. This translates to 5% more speed versus N3P at drive voltage of 1.2V, with the same improved chip density as N3P. N3X will enter volume production in 2025.
  • Today, TSMC introduced the industry’s first Auto Early technology on 3nm, called N3AE. Available in 2023, N3AE offers automotive process design kits (PDKs) based on N3E and allow customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025.

TSMC N3 will be talked about for many years. Not only did TSMC execute as promised, the competition did not, so it really is a perfect semiconductor storm. The result being a very N3 focused industry ecosystem that will be impossible to beat, absolutely.

Here are the TSMC N2 accomplishments from the media briefing:

  • N2 volume production is targeted for 2025; N2P and N2X are planned for 2026.
  • Performance of the nanosheet transistor has exceeded 80% of TSMC’s technology target while demonstrating excellent power efficiency and lower Vmin, which is a great fit for the energy-efficient compute paradigm of the semiconductor industry.
    • TSMC has exercised N2 design collateral in the physical implementation of a popular ARM A715 CPU core to measure PPA improvement: Achieved a 13% speed gain at the same power, or 33% power reduction at the same speed at around 0.9V, compared to the N3E high-density 2-1 fin standard cell.
  • Part of the TSMC N2 technology platform, a backside power rail provides additional speed and density boost on top of the baseline technology.
    • The backside power rail is best suited for HPC products and will be available in the second half of 2025.
    • Improves speed by more than 10-12% from reducing IR drop and signal RC delays.
    • Reduces logic area by 10-15% from more routing resources on the front side.

Remember, N2 is nanosheets, which, unlike FinFETs, is not open source technology so this is really going to be a challenge for design and the supporting ecosystem which gives TSMC a very strong advantage. TSMC also mentioned what follows nanosheets which I found quite interesting. I’m sure we will hear more about this at IEDM 2023:

  • Transistor architecture has evolved from planar to FinFET and is about to change again to nanosheet.
  • Beyond nanosheet, TSMC sees vertically stacked NMOS and PMOS, known as CFET, as one of the key process architecture choices going forward.
    • TSMC estimates the density gain would fall between 5 to 2X after factoring in routing and process complexity.
  • Beyond CFET, TSMC made breakthroughs in low dimensional materials such as carbon nanotubes and 2D materials which could enable further dimensional and energy scaling.

For the record, TSMC has deployed 288 distinct process technologies and manufactured 12,698 products for 532 customers and counting. There is no stopping this train so you might as well jump on with the rest of the semiconductor industry.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5


TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 1
by Daniel Nenni on 04-26-2023 at 6:00 pm

Advanced Technology Roadmap

The TSMC 2023 North America Technology Symposium happened today so I wanted to start writing about it as there is a lot to cover. I will do summaries and other bloggers will do more in-depth coverage on the technology side in the coming weeks. Having worked in the fabless semiconductor ecosystem the majority of my 40 year semiconductor career and writing about it since 2009 I may have a different view of things than the other media sources so stay tuned.

First some items from the opening presentation. As I have mentioned before, AI is driving the semiconductor industry and North America is leading the way with a reported 43% of the world wide AI business. With AI you have 5G since tremendous amounts of data have to be both processed and communicated from the edge to the cloud and back again and again and again.

Due to this tremendous industry driver, TSMC expects the global semiconductor market to approach $1 trillion by 2030 as demand surges from HPC-related applications with 40% of the market, smartphone at 30%, automotive at 15%, and IoT at 10%.

Of course in 2023 we will experience a revenue pothole which C.C. Wei joked about. C.C. said he would not give a forecast this year since he was wrong in saying TSMC would again experience double digit growth in 2023. It is now expected to be single digit decline and it could be even worse than that if you believe other industry sources. Since the TSMC forecast is derived from customer forecasts they were wrong too, there is plenty of blame to share and joke about, which C.C. did.

I still blame the pandemic for the horrible forecasting of late, truly a black swan event. Personally I think the foundry business and TSMC specifically is in the strongest position today so I have no worries whatsoever.

I had flashbacks to when Morris Chang spoke at the symposiums during the C.C. Wei presentation. I see a lot of Morris in C.C. but I also see a very focused man who is not afraid to ask for purchase orders. I also see a much stronger competitive nature in C.C. and I would never want to be on the wrong side of that, absolutely.

“Our customers never stop finding new ways to harness the power of silicon to create innovations that shall amaze the world for a better future,” said Dr. C.C. Wei, CEO of TSMC. “In the same spirit, TSMC never stands still, and we keep enhancing and advancing our process technologies with more performance, power efficiency, and functionality so their pipeline of innovation can continue flowing for many years to come.”

I sometimes tell my family that I don’t want to talk about my accomplishments because it will seem like bragging and I’m much too humble to brag. This is actually true with TSMC so here are some of their accomplishments from the briefing:

  • Together with partners, TSMC created over 12,000 new, innovative products, on approximately 300 different TSMC technologies in 2022.
  • TSMC continues to invest in advanced logic technologies, 3DFabric, and specialty technologies to provide the right technologies at the right time to empower customer innovation.
  • As our advanced nodes evolve from 10nm to 2nm, our power efficiency has grown at a CAGR of 15% over a span of roughly 10 years to support the semiconductor industry’s incredible growth.
  • The CAGR of TSMC’s advanced technology capacity growth will be more than 40% during the period of 2019 to 2023.
  • As the first foundry to start volume production of N5 in 2020, TSMC continues to improve its 5nm family offerings by introducing N4, N4P, N4X, and N5A.
  • TSMC’s 3nm technology is the first in the semiconductor industry to reach high-volume production, with good yield, and the Company expects a fast and smooth ramping of N3 driven by both mobile and HPC applications.
  • In addition, to push scaling to enable smaller and better transistors for monolithic SoCs, TSMC is also developing 3DFabric technologies to unlock the power of heterogeneous integration and increase the number of transistors in a system by 5X or more.
  • TSMC’s specialty technology investment experienced more than 40% CAGR from 2017 to 2022. By 2026, TSMC expects to grow specialty capacity by nearly 50%.

The two customer CEO presentations that followed C.C. were quite a contrast. ADI has been a long and trusted TSMC customer where as Qualcomm has been foundry hopping since the beginning of fabless time. I remember working with QCOM on a 40nm design that was targeted to four different fabs. TSMC did the hard work first then it went to UMC, SMIC, and Chartered for high volume manufacturing.  QCOM has a new CEO and TSMC has CC Wei so that may change. The benefits of being loyal to TSMC have grown dramatically since the planar days so we shall see.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5


TSMC has spent a lot more money on 300mm than you think

TSMC has spent a lot more money on 300mm than you think
by Scotten Jones on 04-06-2023 at 10:00 am

Slide1

Up until November of 2022, IC Knowledge LLC was an independent company and had become the world leader in cost and price modeling of semiconductors. In November 2022 TechInsights acquired IC Knowledge LLC and IC Knowledge LLC is now a TechInsights company.

For many years, IC Knowledge has published a database tracking all the 300mm wafer fabs in the world. Compiled from a variety of public and private sources, we believe the 300mm Watch database is the most detailed database of 300mm wafer fabs available. IC Knowledge LLC also produces the Strategic Cost and Price Model that provides detailed cost and price modeling for 300mm wafer fabs as well as detailed equipment and materials requirements. The ability to utilize both products to analyze a company provides a uniquely comprehensive view and we recently utilized these capabilities to do a detailed analysis of TSMC’s 300mm wafer fabs.

One way we check the modeling results of the Strategic Cost and Price Model is to compare the modeled spending on 300mm fabs for TSMC to their reported spending. Since the early 2000s nearly all of TSMC’s capital spending has been on 300mm wafer fabs and the Strategic Model covers every TSMC 300mm wafer fab.

Figure 1 presents an analysis of TSMC’s cumulative capital spending by wafer fab site from 2000 to 2023 and compares it to the reported TSMC capital spending.

Figure 1. TSMC Wafer Fab Spending by Fab.

In figure 1 there is a cumulative area plot by wafer fab calculated using the Strategic Cost and Price Model – 2023 – revision 01 – unreleased, and a set of bars representing TSMC’s reported capital spending. One key thing to note about this plot is the Strategic Cost and Price Model is a cost and price model and fabs don’t depreciate until they are put on-line, therefore the calculated spending from the model is for when the fabs come on-line whereas the reported TSMC spending is when the expenditure is made regardless of when it comes on-line. TSMC’s capital spending also includes some 200mm fab, and mask and packaging spending. The TSMC reported spending is adjusted as follows:

  1. In the early 2000s estimated 200mm spending is subtracted from the totals. In some cases, TSMC announced what portion of capital spending was 200mm. In the overall cumulative total through 2022 this is a not a material amount of spending.
  2. Recently roughly 10% of TSMC’s capital spending is for masks and packaging, TSMC discloses this and it is subtracted from the total.
  3. When capital equipment is acquired but not yet put on-line, it is accounted for as assets in progress and this number is disclosed in financial filings. We subtract this number from the reported spending because the Strategic Model calculates on-line capital.

Note that fabs 12 and 20 are/will be in Hsinchu – Taiwan, Fabs 14 and 18 are in Tainan – Taiwan, Fab 15 is in Taichung – Taiwan, Fab 16 is in Nanjing – China, Fab 21 is in Arizona – United States, Fab 22 is planned for Kaohsiung – Taiwan and Fab 23 is being built in Kumamoto – Japan.

Some interesting conclusions from this analysis:

TSMC has spent roughly $135 billion dollars on 300mm wafers fabs through 2022. This number should break $200 billion dollars in 2024.

Fab 18 is TSMC’s most expensive fab (5nm and 3nm production), we expect that site to exceed $100 billion dollars in investment next year. Interestingly Fab 18 is right next to Fab 14 where an investment of more than $30 billion dollars has taken place and the combination next year will approach $140 billion dollars!

The capital investment of roughly $135 billion dollars in 300mm fabs just by TSMC is an amazing number, perhaps even more amazing is the investment is accelerating, should break $200 billion dollars in 2024 and could break $400 billion dollars by 2030.

Customers that license our 300mm Watch channel not only get the 300mm watch database along with regular updates, they also get access to this recent TSMC analysis and will also get access to a similar analysis we are doing of Samsung. For information on the 300mm Watch database or Strategic Cost and Price Model please contact sales@techinsights.com

Also Read:

SPIE Advanced Lithography Conference 2023 – AMAT Sculpta® Announcement

IEDM 2023 – 2D Materials – Intel and TSMC

IEDM 2022 – TSMC 3nm

IEDM 2022 – Imec 4 Track Cell


3DIC Physical Verification, Siemens EDA and TSMC

3DIC Physical Verification, Siemens EDA and TSMC
by Daniel Payne on 02-07-2023 at 10:00 am

3DIC min

At SemiWiki we’ve written four times now about how TSMC is standardizing on a 3DIC physical flow with their approach called 3Dblox, so I watched a presentation from John Ferguson of Siemens EDA to see how their tool flow supports this with the Calibre tools. With a chiplet-based packaging flow there are new physical verification challenges, so the response at Siemens EDA was to develop Calibre 3DSTACK, which supports 3DIC and enables thermal analysis.

2.5DIC Interconnect

Physical checks for DRC ensure that substrate interfaces are correct with: alignment, overlaps, scaling and die-to-die spacings. LVS checking determines if connectivity through the interposer or package RDL are correct, compared to the golden netlist. Even the parasitics formed through the packaging interconnect need to be extracted and analyzed, as it impacts signal integrity and timing margins.

3D DRC and LVS

An early approach at 3DIC for LVS verification was to run it separately for each die to die interface, but that is impractical, instead the approach used with Calibre 3DSTACK is to check the full assembly, both DRC and LVS, with one deck, using one run.

To actually design and plan your 3DIC package assembly there’s another Siemens EDA tool called Xpedition Substrate Integrator (XSI), and that allows you to create the heterogeneous rule file, plus generate the source netlist. 3DIC package design and verification tools are shown below:

XSI and Calibre 3DSTACK

TSMC supplies the Assembly Design Kits (ADK) to support their 3Dblox tool flow, where it’s like a LEF/DEF flow, but in 3 dimensions now.

3Dblox package

Physical verification checking using the 3Dblox format is automated in this tool flow with Calibre 3DSTACK, and is independent of which tool creates the 3Dblox data.

3Dblox to Calibre 3DSTACK tool flow

In addition to 3DIC physical verification, there are new reliability issues like thermal, as the chiplets are placed in closer proximity. Temperature increases slow down silicon switching times and shorten semiconductor lifespan, which could lead to a timing or reliability failure. To find out how the package assembly impacts each chiplet, there’s another Siemens EDA tool, Simcenter Flotherm, to support the development of a thermal digital twin. With this you can get fast analysis, while in the early planning steps. Analysis results as static or dynamic heat maps are shown at the assembly, die or IP level. You can even get a post-layout netlist with the temperature coefficients of each device, which is used for signal integrity and timing analysis.

Simcenter Flotherm flow

Starting from a 3Dblox file, this thermal flow uses a 3DSTACK syntax, creating individual chip power maps across the assembly. Engineers will see wave forms or animated heat maps of the temperatures, or power can be shown at the chip or assembly level. Constraints can be specified, and then during thermal simulation any warnings or failures are noted.

Calibre and 3Dblox thermal flow

Adding thermal capabilities to support 3DIC packaging at Siemens EDA required close collaboration with TSMC.

Summary

The market excitement of 3DIC design also brings about new technology challenges, like how to perform physical verification with DRC and LVS in the most efficient method. TSMC has standardized in one format, the physical stacking and logic connectivity information, calling it 3Dblox. Siemens EDA with Calibre 3DSTACK fully supports the 3Dblox format in their DRC and LVS flows. Designing and planning 3D package assemblies is done with XSI, and new thermal analysis also uses the 3Dblox format. Thermal analysis for 3DIC packaging is also possible, allowing products to be designed to meet reliability goals.

The EDA, foundry and IP communities have collaborated together to face the new 3DIC design and verification challenges, allowing our economy to enjoy a steady stream of new products that are now reaching 100 billion transistors. The future of 3DIC is bright indeed.

Related Blogs


Advances in Physical Verification and Thermal Modeling of 3DICs

Advances in Physical Verification and Thermal Modeling of 3DICs
by Peter Bennet on 02-07-2023 at 6:00 am

Fig 1 3DIC

If, like me, you’ve been paying too little attention to historically less glamorous areas of chip design like packaging, you’ll wake up one day and realize just how much things have changed and continue to advance and how interesting it’s become.

One of the main drivers here is the increasing use of chiplets to counter the decreasing – indeed vanishing – cost gains from the latest process shrinks by allowing finer grain mapping of large sub-system blocks to their optimal process technology and optimise block reuse and design resources.

This is the sort of package scenario we’re dealing with (let’s call this an assembly of components).

The expanding world of 2.5D and 3D packaging falls between monolithic chip and PCB design, so both EDA and system level tools must be brought together to automate the process. Tasks like properly automating intra-package connectivity, checking vertical plane connections and more precise thermal modeling.

As with almost everything else in EDA these days, that means ever closer cooperation between EDA tool vendors, manufacturing and designers.

Siemens and TSMC’s work on 3DIC to jointly develop the TSMC 3Dblox standard unified design ecosystem based around Siemens’ Calibre 3DSTACK and c tools is a good example. John Ferguson’s presentation at TSMC OIP last October covered the advances here in both logical and physical verification and thermal analysis. Let’s take a closer look.

Closing the gaps in 3D Physical Verification

There are some obvious challenges here with 3DIC structures.

  • Processes may share layer names, whilst having different characteristics
  • Pin and pad names on components may be equivalent, but use different names
  • Tools need to create a combined PV deck, netlist and physical DB to verify the entire assembly and still maintain the correct rules for individual components
  • Potentially different input file formats for the components.

Packaging with heterogeneous process die creates new challenges for physical verification (PV), mainly in preparing a complete and accurate DB. Calibre 3DSTACK (see diagram below) already handled much of this PV prep – tasks like compiling the assembly physical DB with a single PV deck and computing the correct coupling between stacked die.

Adding Siemens’ Xpedition Substrate Integrator (XSI) planning tool closes the remaining gaps of describing the required components and connectivity (analagous to a spec or custom schematic), creating a merged netlist and managing the design DB; even automating the Calibre 3DSTACK verification.

One thing remains – finding a way to create adequate “library models” and “design rules” for the components. TSMC’s new 3DBlox approach does this with Assembly Design Kits (APDK) to describe the connectivity, process and assembly characteristics and design rules for each component.

Putting this all together we get a flow where can we prepare, run and debug the full assembly PV.

Thermal Analysis

3D packaging also creates greater thermal challenges including:

  • greater interaction between die
  • tougher heat dissipation challenge – greater power density due to 3D stacking
  • modeling vertical thermal gradients becomes necessary
  • modeling heatsink interaction for 3D die

Transistor performance strongly depends on temperature, so such thermal effects cannot be ignored. And these aren’t just signoff checks – we need good thermal and power modeling very early in the design and integrated into the ASIC design flow, since late changes here will create major rework.

With physical verification, the challenge was more one of verifying the top-level and component interfaces. Here it’s more about understanding the impact of the overall system on the components – and then how that feeds back into the top-level system.

A further collaboration with TSMC extended a flow built around the existing Siemens Calibre 3DSTACK and SimCenter Flotherm tools, reusing much of the infrastructure from the PV flow.

Analysis, including static and dynamic heat maps, can be carried out at assembly, die or IP level and power analysis run using mPower. Device temperature coefficients can be extracted for more precise signal and timing analysis.

Summary

Siemens and TSMC have put together a design methodology and flow to support current and future 3DICs based on proven tools (Calibre 3DSTACK and SimCenter Flotherm and with particular attention on simplifying configuration and modeling (3DBlox) and early design use. It’s something that should continue to scale as increasingly sophisticated 3D packaging technology arrives.

It’s also noteworthy that Siemens won a TSMC OIP Partner of the Year award for this work.

Further Information

The TSMC OIP presentation (“TSMC 3Dblox™ simplifies Calibre verification and analysis”) is available until May for readers with the original event registration link and code provided by TSMC.

Find out more about Calibre physical verification and 3DSTACK here:

https://eda.sw.siemens.com/en-US/ic/calibre-design/physical-verification/

https://eda.sw.siemens.com/en-US/ic/calibre-design/physical-verification/3DSTACK/

A white paper “Taking 2.5D/3DIC physical verification to the next level” is also available.

For Siemens Flotherm thermal analysis check here:

https://www.plm.automation.siemens.com/global/en/products/simcenter/flotherm.html

Also Read:

Achieving Faster Design Verification Closure

Siemens Aspires to AI in PCB Design

Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward


IEDM 2022 – TSMC 3nm

IEDM 2022 – TSMC 3nm
by Scotten Jones on 01-02-2023 at 6:00 am

TSMC CPP

TSMC presented two papers on 3nm at the 2022 IEDM; “Critical Process features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond” and “A 3nm CMOS FinFlexTM Platform Technology with Enhanced Power Efficiency and Performance for Mobile SOC and High Performance Computing Applications”.

When I read these two papers prior to the presentations, my initial reaction was the first paper was describing TSMC’s N3 process and the second paper is describing the N3E process, this was confirmed by the presenter during the second presentation.

My second reaction was these papers continue TSMC’s habit of minimizing the amount of technical detail they present. As I discussed about TSMC’s 5nm paper in 2019 here there is minimal critical pitch information and in 2019 all the electrical results were normalized. In these two papers the electrical results are at least in real units, but the first paper only has Contacted Gate Pitch and the second paper only has a minimum metal pitch. I find this very frustrating, the critical pitches will be measured and disclosed as soon as parts hit the open market and insiders and TSMC’s competitors likely already know what they are, I don’t see how presenting a quality technical paper would be a problem. When Intel presented Intel 4 at the VLSI Technology Symposium last year they presented an excellent paper with all of the key data (I wrote about that paper).

N3 Paper

In the first paper, a Contacted Gate Pitch (Contacted Poly Pitch, CPP as I describe it) of 45nm is disclosed. CPP is made up of Gate Length (Lg), Contact to Spacer Thickness (Tsp), and Contact Width (Wc), as illustrated in figure 1.

Figure 1. CPP.

From figure 1. We can see TSMC has been reducing CPP for each new node by reducing all three elements that make up CPP. Logic designs are done by using standard cells and CPP is a major driver of standard cell width, therefore shrinking CPP is a key part of improving density for a new node.

Minimum Lg is a function of gate control of the channel, for example moving from single gate planar devices with unconstrained channel thickness to FinFETs with 3 gates surrounding a thin channel enabled shorter Lg. Gate control of a FinFET is weakest at the base of the fin and optimization is critical. Figure 2 illustrates DIBL versus Lg for multiple TSMC nodes and also how optimizing the fin reduced DIBL for the current work.

Figure 2. DIBL versus Lg.

The second element in shrinking CPP is the Tsp thickness. Reducing Tsp drive up parasitic capacitance unless the spacer is optimized to lower the k value. Figure 3 illustrates TSMC’s investigation of low-k spacers versus an air gap spacer. TSMC found that a low-k spacer was the best solution for scaled CPP.

Figure 3. Contact to Gate Spacer.

The final element of CPP is contact width. In this work an optimized self-aligned contact (SAC) scheme was developed that provided lower contact resistance. The left side of figure 4 illustrates the SAC and the right side illustrates the resistance improvement.

Figure 4. Self-Aligned Contact.

This work enabled the N3 process with a high-density SRAM size of 0.0199μm2. This work will also be important as TSMC moves forward to their 2nm process. At 2nm TSMC is going to move to a type of gate-all-around (GAA) architecture known as a horizontal nanosheet (HNS) and HNS enables shorter Lg (4 gates instead of three surrounding a thin gate), but Wc and Tsp will still have to be optimized.

N3E

The N3E process is described by TSMC as an enhanced version of N3, interestingly N3E is believed to implement relaxed pitches versus N3, for example CPP, M0 and M1 are all believed to be relaxed for performance and yield reasons. There are varying stories about TSMC N3 and whether it is on time or not. The way I look at it is N5 entered risk starts in 2019 and by Christmas 2020 there were Apple iPhones in store with N5 chip. N3 entered risk starts in 2021 and iPhones won’t hit the market with N3 chips until next year. In my view the process is at least 6 months late. In this paper a high-density SRAM cell size of 0.021 μm2 is disclosed. Larger than the N3 SRAM cell of 0.0199 μm2. The yields for N3 are generally described as being good with 60% to 80% mentioned.

There are two major features of this process discussed in this paper:

  1. FinFlexTM
  2. Minimum metal pitch of 23nm with copper interconnect with an “innovative” liner for low resistance.

FinFlexTM is a kind of mix and match strategy with double height cells that can be 2 fins cells on top with 1 fin cells on the bottom for maximum density, 2 fin cells over 2 fin cells as kind of mid performance and density and 3 fin cells over 2 fin cells for maximum performance. This give designers a lot of flexibility to optimize their circuits.

Figure 5 illustrates the various FinFlexTM configurations and figure 6 compares the specifications for each configuration to a standard 2 over 2 fin cell at 5nm.

Figure 5. FinFlexTM cells.

 

Figure 6. 3nm FinFlexTM cell performance versus 5nm cells.

 A plot in this paper is the via resistance distribution for the 15 level metal stack at approximately 550 ohms. In current processes power comes in through the top of the metal stack and has to travel through the via chain down to the devices, 550 ohms in a lot of resistance in a power line. This is why Intel, Samsung and TSMC have all announced backside power delivery for their 2nm class processes. With extreme wafer thinning the vias bringing power in from the backside should offer a >10x improvement in via resistance.

Comparisons

One question you may have as a reader is how this process compares to Samsung’s 3nm process. TSMC is still using FinFETs while Samsung has transitioned to GAA – HNS they call multibridge.

At 5nm by our calculations TSMC’s densest logic cells are 1.30x the density of Samsung’s densest logic cells. If you look at TSMC density values in figure 6., the 2-2 fin cells are 1.39x denser than 2-2 cells in 5nm, and the 2-1 cells offer a 1.56x density improvement. Samsung has two versions of 3nm with the SF3E (3GAE) version 1.19x denser than 5nm and the SF3 (3GAP) version 1.35x denser than 5nm, falling further behind TSMC’s industry leading density. I also believe TSMC has better performance at 3nm and slightly better power although Samsung has closed the power gap likely due to the HNS process.

Also Read:

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

Does SMIC have 7nm and if so, what does it mean

SEMICON West 2022 and the Imec Roadmap