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Circuit Simulation update from Cadence at DAC

Circuit Simulation update from Cadence at DAC
by Daniel Payne on 06-17-2011 at 6:06 pm

Intro
In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what’s new with circuit simulation at DAC this year.

Notes

News – market is growing, RF CMOS simulation is growing
– Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
Recent news withRead More


Reduced IC leakage at DAC

Reduced IC leakage at DAC
by Daniel Payne on 06-17-2011 at 5:46 pm

Intro
Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.

Notes

Why do this?
– Reduce leakage
– Increase gate lengths on paths with slack
–… Read More


Cadence spinout at DAC

Cadence spinout at DAC
by Daniel Payne on 06-17-2011 at 5:37 pm

Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired… Read More


RLCK reduction tool at DAC

RLCK reduction tool at DAC
by Daniel Payne on 06-17-2011 at 5:23 pm

Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.


Daniel Borgraeve (on right)

Notes
Edxact
– Started seven years ago… Read More


Ciranova Update at DAC

Ciranova Update at DAC
by Daniel Payne on 06-17-2011 at 4:55 pm

Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.

Notes
New in 2011
– New GUI with schematic, layout and constraints
o Cross probing between all three windows
– Schematic for constraint entry
o Can start with a blank… Read More


EDA Interoperability at DAC

EDA Interoperability at DAC
by Daniel Payne on 06-17-2011 at 4:42 pm

Intro
My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.

Notes
Interconnect Modeling- Open Source Interconnect Technology Format (ITF)o Used by Star RC

–… Read More


One Trillion Transistor IC Layout at DAC

One Trillion Transistor IC Layout at DAC
by Daniel Payne on 06-17-2011 at 4:20 pm

Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.


Karen Mangum

Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
–… Read More


Berkeley Design Automation at DAC

Berkeley Design Automation at DAC
by Daniel Payne on 06-17-2011 at 4:01 pm

Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).

Notes

Quarterly release: 2011 Q2 now

Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

Device Noise – three … Read More


GlobalFoundries Production-Ready @ 28nm in Multiple Locations!

GlobalFoundries Production-Ready @ 28nm in Multiple Locations!
by Daniel Nenni on 06-15-2011 at 11:02 am

GLOBALFOUNDRIES showed off its 28nm design ecosystem at #48DAC last week in San Diego. The company featured a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership… Read More


Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm

Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.


Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More