One Trillion Transistor IC Layout at DAC

One Trillion Transistor IC Layout at DAC
by Daniel Payne on 06-17-2011 at 4:20 pm

Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.

Karen Mangum

I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
– New for 2011: 3D Floor planner
o Mostly a manual process to do TSV on two or more stacked dies
o 3D Floorplanner automatically finds all thos places
o Autoplace 3D vias (placed on edges in this demo because of density of SRAM on top of processor)
o Demo with 3 stacked die, also autoplace 3D vias
o Tezzaron – customer using Max 3D, designing 3D stacked wafer designs. Doing a 7 stacked chip design.
o 3D DRC – Magma has a tool, you can launch Magma inside of Max-3D and view the results interactively
o Pricing:?

OA – we can read and write it

Large designs – Virtuoso cannot move or work on the largest designs, so it’s time to consider using Max or Max-3D

Max – demo with 1 trillion MOS devices at DAC this year
– Tezzaron read in 100GB GDS II layout database into Max

Customers – Most will not be mentioned because of corporate policy.

We all know that the big three EDA companies have IC layout editors (Cadence, Synopsys, Mentor) but this lesser known EDA company has capacity and 3D features that I don’t see anywhere else.

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