How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROIAs computing expands from data centers to edge…Read More
Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V CoresAkeana Inc. announced a key milestone in the…Read More
An AI-Native Architecture That Eliminates GPU InefficienciesA recent analysis highlighted by MIT Technology Review…Read More
Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon SecurityIn a significant advancement for the semiconductor industry,…Read More
Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic EngineeringAt the 2026 Chiplet Summit, Synopsys presented a…Read More
The fundamental economics of the semiconductor industry are summed up in the phrase “fill the fab.” Building a fab is a major investment. With a lifetime of just a few years, the costs of owning a fab are dominated by depreciation of the fixed capital assets (the building, the air and water purification equipment, the manufacturing… Read More
I used my secret powers (being a blogger will get you a press pass) to go to the first day of the SPIE conference on advanced lithography a couple of weeks ago. Everything that happens to with process nodes seems to be driven by lithography, and everything that happens in EDA is driven by semiconductor process. It is the place to find … Read More
During DVCon I met with Steve Bailey to get an update on Mentor’s verification. They were also announcing some new capabilities. I also attended Wally Rhines keynote (primarily about verification of course, since this was DVCon; I blogged about that here) and the Mentor lunch (it was pretty much Mentor all day for me) on the… Read More
Clock gating is one of the most basic weapons in the armoury for reducing dynamic power on a design. All modern synthesis tools can insert clock gating cells to shut down clocking to registers when the contents of the register are not changing. The archetypal case is a register which sometimes loads a new value (when an enable signal… Read More
Formal verification can be used for many things, but one is to ensure that synthesis performs correctly and that the behavior of the output netlist is the same as the behavior of the input RTL. But designs are getting very large and formal verification is a complex tool to use, especially if the design is too large for the formal tool… Read More
Image sensors are all around us with the cell phone being a popular example, and 35mm DSLR camera being another one. Last week I spoke with Kenton Veeder, an engineer at Senseeker that started his own image sensor IP and consulting services company. Instead of focusing on the consumer market, Kenton’s company does sensor … Read More
Cavium designs some very complex SoCs containing multiple ARM or MIPS cores at 32 and 64 bit. This complexity leads to major challenges in validating the overall chip architecture to ensure that their designs will meet the requirements of their customers once they are completed, with performance as high as 100Gbps.
Cavium have… Read More
FinFETs are fun! They certainly have kept me busy writing over the past year about the possibilities and probabilities of a disruptive technology that will dramatically change the semiconductor ecosystem. Now that 14nm silicon is making the rounds I will be able to start writing about the realities of FinFETs which is very exciting!… Read More
Those of us who spend a lot of time at EDA marketing events cannot help but notice the dramatic shrinking of the floor space, and to some extent attendance, at the major EDA shows such as DAC and DATE. DAC used to occupy both the north and south halls of Moscone Center when in San Francisco, but now only takes up one hall. So, I did not have… Read More
Back in 2011, TSMC announced it was extending its IP Alliance Program to include soft, or synthesizable IP. Around that time it was also announced that Atrenta’s SpyGlass platform would be used as the sole analysis tool to verify the completeness and quality of soft IP before being admitted to the program. Since then, the … Read More
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Memory Matters: Signals from the 2025 NVM Survey