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Can Japan Regain Semiconductor Leadership?

Can Japan Regain Semiconductor Leadership?
by Paul McLellan on 02-25-2013 at 1:14 pm

In the 1980s, Japan was seen as the leader in the semiconductor industry. Their quality was higher, especially in memories, and the US was worried about falling behind. In fact Sematech was created in 1987 by the US government and a consortium of 14 US-based semiconductor companies primarily to pool investment on common problems… Read More


The New "Mobile Foundry" Era: Whose Wheelhouse?

The New "Mobile Foundry" Era: Whose Wheelhouse?
by Ed McKernan on 02-25-2013 at 1:12 pm

Nothing seems to raise the Visceral Ire of Semiwiki readers like the two words: Intel and Foundry. To get maximum steam coming out of the ears make sure you combine the two words in a sentence. Something along the lines like: Intel is Now Going to be a Leader in the Foundry Business. Pause…..Ok catch your breadth and now let’s move on … Read More


Who Allegedly Broke Tela’s Patents: Is Samsung or Qualcomm the Real Villain?

Who Allegedly Broke Tela’s Patents: Is Samsung or Qualcomm the Real Villain?
by Randy Smith on 02-25-2013 at 1:08 pm

I recently blogged about the actions filed by Tela Innovations at both the US International Trade Commission (USITC) and in federal district court. Those actions allege that five mobile phone manufacturers -HTC, LG, Motorola Mobility, Pantech, and Nokia – were importing handsets into the US which infringed on seven of… Read More


Learning Properties, Assertions and Covers for Hardware Design

Learning Properties, Assertions and Covers for Hardware Design
by Daniel Payne on 02-25-2013 at 12:10 pm

How do you learn new hardware design topics? I just got trained online about property-based verification for hardware designers using a free online class at Aldec. The material was created by Jerry Kaczynski, a Research Engineer at Aldec.

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FinFET Design Challenges at 14nm and 10nm

FinFET Design Challenges at 14nm and 10nm
by Daniel Payne on 02-25-2013 at 11:09 am

speaker vassiliosgerousis

At DAC 2012 we were hearing about the 20nm design ecosystem viability, however IC process technology never stands still so we have early process development going on now at the 10nm and 14nm nodes where FinFET technology is being touted. Earlier in February Vassilios Gerousis, a distinguished engineer at Cadence presented a session… Read More


At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT
by Graham Bell on 02-24-2013 at 8:10 pm

By now, you will have seen several postings about all the different activities that are going on at Design and Verification Conference being held Feb. 25-28 at its usual location – the DoubleTree Hotel in San Jose, CA. Besides organizing an experts panel “Where Does Design End and Verification Begin?“, Real… Read More


MUST: DSP ready solution for tomorrow smartphone based on CEVA-XC 4000

MUST: DSP ready solution for tomorrow smartphone based on CEVA-XC 4000
by Eric Esteve on 02-24-2013 at 5:13 am

Like Guiness dark beer, competition is good for you! I mean good for end user, as it pushes DSP IP supplier to provide ever better solution. I am not talking about me-to type of competition, like that we have seen in the past with IBM trying to displace TI at Nokia, by offering a LEAD (DSP IP core from TI used in every NOKIA wireless phone… Read More


How Can You Work Better with Your Foundry?

How Can You Work Better with Your Foundry?
by glforte on 02-22-2013 at 5:40 pm

The fabless revolution in the digital semiconductor industry is no more, with just a few integrated device manufacturers (IDMs) remaining on the playing field, it is now the normal way to do business. However, the learning curve for each new process node continues as it always has, with a host of new technical challenges for the … Read More


Is debugging a task, or a continuous process?

Is debugging a task, or a continuous process?
by Don Dingee on 02-22-2013 at 2:59 pm

Early in my so-called EE career, I sat in a workshop led by the director of quality for the Ford truck plant in Louisville, KY, where “Quality is Job #1.” At that time, they were gaining experience in electronic control modules (ECMs) for fuel efficiency and emissions control. Who better to transfer the secrets of Crosby and Deming… Read More


Modeling TSV, IBIS-AMI and SERDES with HSPICE

Modeling TSV, IBIS-AMI and SERDES with HSPICE
by Daniel Payne on 02-21-2013 at 8:10 pm

The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively.… Read More