A Recipe for Performance Optimization in Arm-Based SystemsAround the mid-2000’s the performance component of Moore’s…Read More
Synopsys Accelerates Innovation on TSMC Advanced ProcessesWe all know that making advanced semiconductors is…Read More
Tools for Chips and Dips an Overview of the Semiconductor Tools MarketFrom humble beginnings in military applications, the semiconductor…Read More
How Samtec Helps Achieve 224G PAM4 in the Real World224 Gbps PAM4 gets attention for applications such…Read More
SoC Power Islands Verification with Hardware-assisted VerificationThe ever-growing demand for longer battery life in…Read More
Even though most of us have witnessed the emergence of the fabless semiconductor industry it is still good to go back and remember how we got to where we are today, to realize that the semiconductors that you now hold in your hand were enabled by the rise of the fabless semiconductor business model. This is the first in a series of blogs… Read More
Consolidation continues in the EDA industry with Synopsys announcing today that they acquired Ciranova, a provider of software to automate custom IC layout. Remember that Synopsys invested in Ciranova back in March 2008 and September 2010 (along with Intel Capital, Mentor Graphics and Alloy Ventures), so this deal has some … Read More
Not yet a year into Rory Read’s term and the AMD board must be considering that the value of the x86 patents and engineering talent is worth much more than the stocks $3B valuation and easier to fathom putting on the auction block than continuing to sell $25 processors into the back channels of China and the Developing World. As I read… Read More
The SystemVerilog standard defines an X as an “unknown” value which is used to represent when simulation cannot definitely resolve a signal to a “1”, a “0”, or a “Z”. Synthesis, on the other hand, defines an X as a “don’t care”, enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often… Read More
The Wi-Fi Alliance is an industry consortium dedicated to driving adoption of the various Wi-Fi standards which also go under the rather less catchy name of IEEE 802.11x (where the x varies depending on the generation of the standard, right now a, b, g or n). They also certify devices for interoperability.
Wi-Fi Alliance says that… Read More
About 4 years ago some of my semiconductor cohorts urged me to blog. “Hey Dan, you’re a funny guy, write about EDA and IP, make us laugh!” Of course what I think is funny most people think is snarky, which is a nice word for being a smart ass. The traditional semiconductor press was crumbling, the non traditional EDA websites were outdated,… Read More
The concept of Non Volatile Memory (NVM) block which could be integrated into an ASIC is relatively recent, Novocell for example has been created in 2001. NVM IP integration into an ASIC is a pretty smart technology: integrating from a few bytes to up to Mbits into a SoC can help reducing the number of chips in a system, increase security… Read More
Optimizing logical, physical, electrical, and manufacturing effects, Cadence digital implementation technology eliminates iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start. … Read More
Josefina Hobbs, a solutions architect at Synopsys, demonstrates protocol debug made easy using the Synopsys Protocol Analyzer. This gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. The video also shows the integration of Synopsys Protocol Analyzer with SpringSoft’s… Read More
I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More
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Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM