WP_Term Object
(
    [term_id] => 45
    [name] => Aldec
    [slug] => aldec
    [term_group] => 0
    [term_taxonomy_id] => 45
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 96
    [filter] => raw
    [cat_ID] => 45
    [category_count] => 96
    [category_description] => 
    [cat_name] => Aldec
    [category_nicename] => aldec
    [category_parent] => 157
    [is_post] => 1
)

Locked on FPGA design brand recognition

Locked on FPGA design brand recognition
by Don Dingee on 02-28-2014 at 3:30 pm

Back in the days where computing was dominated by a few big (and now mostly dearly departed) names, there was a saying: “Nobody ever got fired for buying IBM.” The relative safety of immediate brand recognition, especially among non-technical upper management, dissuaded many users from recommending or even seeking out other options. Non-justification was just easier.

Technology changed, but people haven’t. Many users still make tech buying decisions based on risk-aversion instead of innovation, preferring to stand in line with the crowd even if we’re not quite sure what it is we are waiting for – but it must be good, because everyone important is here. Apple uses this effect to cause people to repeatedly stand in queues for iPhone and iPad launches, long after the initial burst of disruption wore off.

 Photo credit: Adrees Latif / REUTERS

More often than not, I find myself subscribing to the Yogi Berra counterpoint: “Nobody goes there anymore, it’s too crowded.” But for most tech users, there is safety in numbers, especially considering options with low numbers tend to disappear quickly. The risk of the unknown can trump exploration of new technology.

Fortunately, in the age of the startup, venture capital, fabless technology, and social media, the mainstream choices usually are pretty good because they have to be for long-term survival. No company can afford to sit on their laurels for more than a brief moment of celebration; there are way too many competitors pounding at the gate. Good tech products have to evolve to stay competitive, and bad tech products or lousy customer support get clobbered on social media faster than Ronda Rousey challengers.

I was resolving final comments on a white paper for a client this week. In it, I made a generic statement there are many tools out there for FPGA synthesis, mentioning SystemC as one of the approaches designers may want to consider. The comment, which I greatly appreciate, came back:

[Xilinx] Vivado HLS is much more prevalent than SystemC.

That got me thinking. No disparaging Xilinx or Vivado Design Suite technology or popularity here; it’s a great tool. The latest versions of Vivado do have high level synthesis capability, and most embedded engineers are far more familiar with C/C++ algorithms and probably would like to use them directly if possible in FPGA designs.

We can debate the pros and cons of FPGA synthesis strategies, and the validity of the comment, another time. What I found interesting was the motivation behind it, and the immediate leap from methodology options to a tool choice, a very safe one at that. Nobody ever got fired for using Xilinx tools with Xilinx parts, right?

If your world begins and ends with Xilinx FPGAs, that’s OK. But, like the mainframe biz of yore, things could change. You could change jobs. You could get a new requirement, something exotic like rad hard or some funky interface. Your customer could tell you what FPGA you’re going to use, because changing their IP for another part is risk they don’t want. Or a myriad of other reasons to look at your options. (BTW, this all applies if you use some other FPGA architecture; you may have to switch to Xilinx at some point.)

You’ll walk in the office of some PHB where you work, and the conversation will go like this:
You: “Hey boss, I need you to sign this purchase order for Aldec Active-HDL.”

PHB: “Who’s Aldec? I thought we used Xilinx.”

You: “They’ve been in business 30 years selling vendor independent EDA tools, and they’ve got some great solutions for FPGAs we should try. I downloaded their evaluation and …”

PHB: “Yeah. But, is it safe?” (Google it.)


At this point, you could run before the anesthesia takes effect, or you could try explaining in terms the PHB would likely not understand, or you could whip out the recent SemiWiki article on Active-HDL from Luke Miller. You see, Luke was introduced to Aldec on a concall I was on in January 2014, downloaded the evaluation – and switched tools on the spot. His likelihood to see multiple FPGA architectures in his role as “The FPGA Expert” consulting to the industry at-large is very high, and he’s seen tools from many vendors.

I’m not suggesting to scream and run away from Xilinx or any other FPGA tools here. I think Xilinx Zynq is huge for the industry. This is just an example of how people lock on brand recognition.

All I’m suggesting is don’t ever let the PHB and his cronies dissuade you from looking at options like Aldec because they aren’t the names they are used to hearing. You might miss innovation that could make the difference in your next design – and then you and the PHB could both get fired. Don’t be that guy or gal.

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