Did you know in the Xilinx Virtex 28nm series you can REALLY run the DSP at 741 MHz? I say ‘really’ as you know dear reader, not all the FPGA claims of speed and usage tends to live up to reality. I cannot stand marketing games where you can run at a GHz ‘But’ and then comes the list of gotcha’s. Don’t believe me? Whaaat? Well let’s take a journey through a REAL example of a Parallel FIR filter that runs in REAL silicon TODAY running the DSP at 741 MHz. By the way, my kids laugh every time I say FIR filter.
Why did the digital filter designer get attacked by ‘People for the Ethical Treatment of Animals’? “He was selling FIRs’.
So let us begin, what is a FIR filter? ‘FIR’ stands for Finite Impulse Response. DSP 101. They are the heart of all digital systems, they cannot live without them. All they do is convolve a steam of data (signal) with weights or coefficients to shape or filer the data. Below is a diagram of the operations. Multiply’s and Add’s or better known as MACs.
The need of Parallel FIR filtering arises when the data rate is the same as the clock rate or often called ‘systolic FIR’. What allows the designer to run at 741 MHz is the architecture of the DSP48 slices in the Xilinx FPGAs. Xilinx’s DSP are the widest and fastest with no games or tricks. I encourage you to read the following DSP user guides from Xilinx.
The results of the parallel, 80 Tap FIR filter is: Target device: V7 160T -3; Resource: 0 LUTs, 2528 FFs, 332 DSP48; Timing: 1.348ns (=742MHz). If you did not need a Parallel FIR, you would only use 40 DSP. Fun stuff!
Let me remind you once again, you can do this today, this is not UltraScale, and this is Xilinx 28nm. Now, there is perception that Xilinx and Altera are fighting it out and it does not matter who is leading and all is well and let’s get some coffee. That is not the case, for me one of the most important jobs I do is recommend what FPGA to use. The silicon choice is extremely relevant and any competent designer knows this. Choosing the wrong FPGA vendor will mean a board design that will cost another $300k and 3 months more of integration time. Having a design in one FPGA verses spilling out into two FPGAs means winning or losing a design bid. Below is a simple DSP compare of Xilinx and Altera at 28nm.
Xilinx Virtex-7 has up to 3600 DSP, 18×25 width @741 MHz. = 2.7 TMACS potential
Altera Stratix-V has up to 3926 DSP, 18×18 width @500 MHz. = 1.9 TMACS potential
(Note: in symmetric mode, the above numbers would be 2X. Xilinx 5.3 TMACs, Altera 3.9 TMACs)
Now, I was conservative here on two fronts, the first are the DSP bit widths, if you needed wider than 18×18 widths, Xilinx has 38% more bit width than Altera + another 800 GMACs. Or when compared to Xilinx, Altera effectively has 1.2 TMACS. Can you tell me that is not important or not relevant? My designs need to run in silicon, not on paper.
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