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Semiconductor Expert Forum

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Xilinx’s UltraScale vs Arria 10 – Non dolet, Paete

Xilinx’s UltraScale vs Arria 10 – Non dolet, Paete
by Luke Miller on 03-18-2014 at 9:30 pm
Categories: FPGA, Xilinx

The DSP48E2 (I do not come up with these names… Could have named it a multiplier thingy) in the Xilinx 20nm UltraScale family (I do not come up with these names… Could of named it Virtex-8, or Luke-8) is simply amazing. Today was good, as I began playing with UltraScale tools and seeing how the DSP checks out. I also encourage you to check… Read More

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Atmel on Tour at AT&T Park

Atmel on Tour at AT&T Park
by Paul McLellan on 03-18-2014 at 5:02 pm
Categories: Foundries

OK, it’s not exactly AT&T park…it’s the parking lot. But they have a huge semi loaded up with lots of cool Atmel stuff to show off some of the things that their customers are doing with their microcontrollers and display technology, primarily focused on the internet of things (IoT). I went down to check it … Read More

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Social Media at Carbon Design Systems

Social Media at Carbon Design Systems
by Daniel Payne on 03-18-2014 at 11:12 am
Categories: EDA

Started in 2002 Carbon Design Systems has ESL (Electronic System Level) modeling and validation tools for complex SoC design. With their software you can:

  • Perform system level model generation of existing and 3rd party IP directly from RTL for use in any virtual platform
  • Do performance analysis & optimization of SoC architectures
… Read More
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Mentor U2U Is On April 10th

Mentor U2U Is On April 10th
by Paul McLellan on 03-17-2014 at 7:19 pm
Categories: EDA, Siemens EDA

If you are a Mentor user, U2U, the Mentor User group is coming up on April 10th. This is an all day event at the DoubleTree. The event is free. Registration starts at 8am and the agenda itself starts at 9am. There is a reception from 5-6pm in the evening.

There are three keynotes. At 9am: Wally Rhines, CEO of Mentor. The Big Squeeze. For … Read More

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A Fill Solution for 20nm at TSMC

A Fill Solution for 20nm at TSMC
by glforte on 03-17-2014 at 5:12 pm
Categories: EDA, Siemens EDA

By Jeff Wilson, Mentor Graphics

We’ve talked about the new requirements for Fill in IC design for advanced nodes in previous blogs on this site. This time I’d like describe the fill solution that Mentor and TSMC have jointly developed to meet the requirements of fill for TSMC’s 20nm (N20) manufacturing process.

The traditional… Read More

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GSA Silicon Summit Is On April 10th

GSA Silicon Summit Is On April 10th
by Paul McLellan on 03-17-2014 at 1:01 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

The annual GSA Silicon Summit is coming up in a few weeks. It is on April 10th at the Computer History Museum. Registration is at 9am and the meeting itself gets started at 9.45am. The summit finishes at 2.15pm. There are three sections during the day, and lunch is provided.

The first section is on Advancements in Nanoscale Manufacturing… Read More

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The Technology to Continue Moore’s Law…

The Technology to Continue Moore’s Law…
by Eric Esteve on 03-17-2014 at 11:59 am
Categories: FD-SOI, Foundries, STMicroelectronics

Can we agree about the fact that the Moore’s law is discontinuing after 28nm technology node? This does not mean that the development of new Silicon technology, like 14nm or beyond, or/and new Transistor architecture like FinFET will not happen. There will be a market demand for chips developed on such advanced technologies: mobile… Read More

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Xilinx & Apache Team up for FPGA Reliability at 20nm

Xilinx & Apache Team up for FPGA Reliability at 20nm
by Pawan Fangaria on 03-17-2014 at 12:00 am
Categories: Ansys, Inc., EDA, FPGA, Xilinx

In this age of SoCs with hundreds of IPs from different sources integrated together and working at high operating frequencies, FPGA designers are hard pressed keeping up the chip reliability from issues arising out of excessive static & dynamic IR drop, power & ground noise, electro migration and so on. While the IPs are… Read More

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Cadence is all about Semiconductor IP!

Cadence is all about Semiconductor IP!
by Daniel Nenni on 03-16-2014 at 9:00 am
Categories: Cadence, EDA

Cadence continues on its quest to be a top semiconductor IP supplier which is a good thing since the semiconductor world now revolves around IP. Cadence CEO Lip-Bu Tan mentioned IP 14 times during his keynote and he was followed by the president of Imagination Technologies and the CEO of recently acquired Tensilica. I was not afforded… Read More