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Jalapeño Hot Chip, Cool Power Bill: OpenAI Turns Up the Heat on AI Inference

Jalapeño Hot Chip, Cool Power Bill: OpenAI Turns Up the Heat on AI Inference
by Daniel Nenni on 09-09-2026 at 2:00 pm

Jalapeño Hot Chip

OpenAI’s Jalapeño is a custom accelerator designed specifically for AI inference, particularly the low-latency, multi-chip workloads behind interactive and agentic systems. Its central idea is that useful performance cannot be reduced to peak floating-point operations or memory bandwidth. What matters is how quickly … Read More


Keysight EDA update at DAC 2026

Keysight EDA update at DAC 2026
by Daniel Payne on 09-09-2026 at 10:00 am

keysight dac2026

On the last day of #DAC2026 I stopped by the Keysight booth to chat with Nilesh Kamdar, GM of EDA Business to get an update. He has spent 27 years in the industry, and this made 25 DAC trips for him. For Keysight the application areas of focus are serving designers of high frequency and high-speed digital, RF, and mm/uwave designs. An … Read More


2026 Ceva Edge Symposium: Building Intelligence Beyond the Cloud

2026 Ceva Edge Symposium: Building Intelligence Beyond the Cloud
by Daniel Nenni on 09-09-2026 at 6:00 am

Ceva Edge Symposium

The 2026 Ceva Edge Symposium will bring together engineers, technology leaders, ecosystem partners, and innovators to explore a major shift in computing: moving artificial intelligence from distant cloud infrastructure into the devices that interact directly with the physical world. Scheduled for November 2 in Hsinchu,… Read More


HBM’s Second Act: When Memory Starts Thinking

HBM’s Second Act: When Memory Starts Thinking
by Admin on 09-08-2026 at 2:00 pm

HBM Base Die Revolution

Samsung’s Hot Chips 2026 presentation, “HBM Base Die: How HBM Will Evolve Using Advanced Logic Processes,” argues that the base die beneath a High Bandwidth Memory stack is about to become far more than a communications layer. Traditionally, an HBM base die mainly connects stacked DRAM dies to a GPU, TPU, or other processor and … Read More


NVIDIA Vera: Rebuilding the CPU for Agentic AI

NVIDIA Vera: Rebuilding the CPU for Agentic AI
by Admin on 09-08-2026 at 10:00 am

No Agent Left Waiting

Source: Jonathon Evans and Polychronis Xekalakis, “NVIDIA Vera CPU,” Hot Chips 2026. Performance figures are NVIDIA claims, and several results were based on preproduction or unofficial testing.

NVIDIA’s Vera CPU is a server processor designed specifically for agentic AI, where language models repeatedly observe, reason,… Read More


Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters

Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters
by Admin on 09-08-2026 at 6:00 am

Fail Safe Frames and Why Chips&Media’s ASIL B Video IP Matters

As vehicles evolve into software-defined, increasingly autonomous platforms, video processing is becoming part of the safety-critical computing chain. Camera feeds support functions ranging from surround-view monitoring and driver assistance to object detection and automated driving. If the hardware processing those… Read More


High-NA EUV Moves From Experiment to Manufacturing

High-NA EUV Moves From Experiment to Manufacturing
by Daniel Nenni on 09-07-2026 at 11:00 pm

HNA EUV Moves into Manufacturing

Intel Foundry and ASML say high-numerical-aperture extreme-ultraviolet lithography has crossed an important boundary: it is no longer only a development tool, but a production technology. At the SPIE Photomask Technology and Extreme Ultraviolet Lithography conference, the companies reported that Intel has processed … Read More


ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance

ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance
by Daniel Nenni on 09-07-2026 at 11:00 pm

ASML and TSMC’s 12 Inch Photomask Initiative

ASML and TSMC’s proposed shift from 6-inch to 12-inch photomasks is an attempt to redesign a critical but often overlooked part of advanced semiconductor manufacturing. Photomasks are precision plates carrying the circuit patterns projected by a lithography scanner onto a silicon wafer. In extreme-ultraviolet lithography,… Read More


AI Memory Gap at DAC 2026

AI Memory Gap at DAC 2026
by Daniel Payne on 09-07-2026 at 10:00 am

AI memory gap

On Tuesday at #DAC2026 I attended the exhibitor presentation, Synopsys: How Silicon Startups are Addressing the AI Memory Gap. Vikram Bhatia from Synopsys introduced the two presentations from Wenbo Yin, SVP of IC Design at TetraMem and R. Scott Hills, VP of Business Development at ANAFLASH. Datacenters consume large amounts… Read More


When Design Gets Faster, the Bottleneck Moves Through the Physical Stack

When Design Gets Faster, the Bottleneck Moves Through the Physical Stack
by Moh Kolb on 09-07-2026 at 6:00 am

Desing fast Bott through physicalstack

AI can compress the path to tape-out. The next challenge is compressing physical realization.

Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.

AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More