The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More
FPGA Prototyping in Practice: Addressing Peripheral Connectivity ChallengesModern chip design verification often encounters challenges when…Read More
An Insight into Building Quantum ComputersGiven my physics background I’m ashamed to admit…Read More
I Have Seen the Future with ChipAgents Autonomous Root Cause AnalysisI have seen a lot of EDA tool…Read More
Arm FCSA and the Journey to Standardizing Open Chiplet-Based DesignI have written before about an inter-chiplet communication…Read MoreFrom Silos to Systems, From Data to Insight: Keysight’s Upcoming Webinar on EDA Data Transformation
In the fast-evolving world of electronic design automation (EDA), where complexity multiplies with every nanometer shrink and AI integration, data silos are the silent killers of innovation. Keysight Technologies, a leader in design and test solutions, tackles this head-on with their webinar “From Silos to Systems,… Read More
Modern Trends in I/O and ESD Design at TSMC OIP
It was very clear at the recent 2025 TSMC OIP Ecosystem Forum that the semiconductor I/O landscape has undergone a profound transformation over the past 25 years, evolving from simple general-purpose input/output (GPIO) cells in 180nm nodes to highly complex, multi-protocol, feature-rich libraries in advanced 16nm and 22nm… Read More
Podcast EP318: An Overview of Axelera AI’s Newest Chip with Fabrizio Del Maffeo
Daniel is joined by Fabrizio Del Maffeo, CEO and co-founder of Axelera AI, a Netherlands-based startup delivering the world’s most powerful and advanced solutions for AI at the edge.
Fabrizio describes the significant momentum Axelera AI has achieved in the market, with over 350 customers. Dan then explores the company’s… Read More
Agentic Bug Localization. Innovation in Verification
Bug localization continues to be a challenge for both bug triage and root-cause analysis. Agentic approaches suggest a way forward. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More
Why chip design needs industrial-grade EDA AI
By Niranjan Sitapure
Artificial intelligence (AI) is reshaping industries worldwide. Consumer-grade AI solutions are getting significant attention in the media for their creativity, speed, and accessibility—from ChatGPT and Meta’s AI app to Gemini for image creation, Sora for video, Sona for music, and Perplexity for web… Read More
Mixel Company Update 2025
Mixel, Inc., a longtime leader in mixed-signal and MIPI® interface IP, entered a new chapter in its history following its acquisition by Silvaco Group, Inc., a global provider of design software and semiconductor IP. The acquisition, completed earlier in 2025, marks a strategic move that combines Silvaco’s deep expertise in… Read More
Cloud-Accelerated EDA Development
By Nikhil Sharma, Sunghwan Son, Paul Mantey
The semiconductor industry faces an unprecedented crisis that threatens the very foundation of technological innovation. According to the latest Siemens EDA / Wilson Research Study, first-silicon success rates have plummeted to just 14%[1]—the lowest figure in more than twenty… Read More
A Tour of Advanced Data Conversion with Alphacore
There is always a lot of buzz about advanced AI workloads at trade shows. How to train them and how to run them. Advanced chip and multi-die designs are how AI is brought to life, so it was a perfect fit for discussion at a show. But there is another side of this discussion. Much of the work going on in AI workloads has to do with processing… Read More
Self-Aligned Spacer Patterning for Minimum Pitch Metal in DRAM
The patterning of features outside a DRAM cell array can be just as challenging as those within the array itself [1]. The array contains features which are densely packed, but regularly arranged. On the other hand, outside the array, the minimum pitch features, such as the lowest metal lines in the periphery for the sense amplifier… Read More



An Insight into Building Quantum Computers