IMGTC Webinar SemiWIki

The Pivotal Moments That Gave Rise to Silicon Valley

The Pivotal Moments That Gave Rise to Silicon Valley
by Admin on 09-30-2026 at 10:00 am

IMAGE 1 Robert Noyce with microscope

The little-known decisions and breakthroughs—and the remarkable role of Robert Noyce—that helped shape the modern semiconductor industry

by Sunil Mehta

When people tell the story of how Silicon Valley came into being, they usually begin with a familiar sequence of events.

The transistor was invented at Bell Labs. William Shockley… Read More


SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters

SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters
by Daniel Nenni on 09-30-2026 at 8:00 am

BigSky 2U + Full Rack Render

SiFive and AMD demonstrated an AI workload that brings together two open technologies: the RISC-V processor architecture and AMD’s ROCm GPU software platform. At the AI Infra Summit on September 15, 2026, the companies showed ROCm 10.0 running on SiFive’s BigSky datacenter development server. SiFive P870-D CPUs served as the… Read More


Quantum Equivalence Checking. Innovation in Verification

Quantum Equivalence Checking. Innovation in Verification
by Bernard Murphy on 09-30-2026 at 6:00 am

Innovation New

Can quantum computing have any relevance to EDA? This month’s paper suggests it might have a role someday, in accelerating one of the most fundamental of EDA algorithms: SAT. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More


Why Advanced Chip Packaging Is Becoming a Design Problem

Why Advanced Chip Packaging Is Becoming a Design Problem
by Daniel Nenni on 09-29-2026 at 2:00 pm

Why Advanced Chip Packaging Is Becoming a Design Problem

As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die… Read More


Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing

Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing
by Lauro Rizzatti on 09-29-2026 at 12:00 pm

image001 (2)

Recently, I had the opportunity to speak with Johann Foucher, founder and CEO of Pollen Metrology, a French company whose journey offers a rare vantage point on how artificial intelligence is reshaping semiconductor manufacturing from the inside out. What makes Pollen Metrology’s story compelling isn’t just … Read More


Managing Power, Performance and Reliability in the Chiplet Era

Managing Power, Performance and Reliability in the Chiplet Era
by Kalar Rajendiran on 09-29-2026 at 10:00 am

Test Drivers proteanTecs (Chiplet Webinar)

Next-gen AI accelerators, high-performance processors, and complex computing architectures depend heavily on advanced packaging. Bringing multiple dies, chiplets, high-bandwidth memory, and advanced interconnects together into a single 2.5D or 3D package yields massive performance gains. However, this design evolution… Read More


Siemens and TSMC push AI deeper into chip design

Siemens and TSMC push AI deeper into chip design
by Daniel Nenni on 09-29-2026 at 8:00 am

Siemens and TSMC push AI deeper into chip design

Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from… Read More


Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?

Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?
by Moh Kolb on 09-29-2026 at 6:00 am

AgentiC AI SemiWIKI sept21

Agentic AI is beginning to move semiconductor engineering beyond copilots and isolated task automation.

From Agentrys’ public material and recent discussion, its architecture points toward a broader engineering flow:

Specification → RTL → verification → synthesis / physical design → PPA optimization → physical verification… Read More


TSMC OIP Ecosystem Forum 2026: Opening Remarks

TSMC OIP Ecosystem Forum 2026: Opening Remarks
by Mike Gianfagna on 09-28-2026 at 12:00 pm

TSMC OIP Ecosystem Forum 2026 Opening Remarks

The 2026 TSMC Open Innovation Platform (OIP) Ecosystem Forum was held on September 23, 2026, in Santa Clara, CA. This is the event where TSMC showcases the substantial progress made with its massive semiconductor ecosystem. As one would expect, AI was a key topic throughout the day, with some very impressive results reported and… Read More


LLM-assisted schematic test-report analysis and root-cause investigation

LLM-assisted schematic test-report analysis and root-cause investigation
by Admin on 09-28-2026 at 10:00 am

schematic report workflow white (1)

By Piyush Bag

Intro: In this AI era, building data centers has become crucial not just for hyperscalers, but for many companies as well, as they build the infrastructure for AI. At a high level, a data center includes compute, storage, networking, and other infrastructure. This article is about the design lifecycle of network hardware.… Read More