Executive Interview with Victor Lopez of RaiderChip

 

Victor Lopez is Co-Founder and CTO at RaiderChip, with over 20 years of experience in FPGA and ASIC design. Throughout his career, he has led the development of semiconductor IP and custom hardware solutions licensed by international companies in sectors such as defense, aerospace, automotive and professional video, specializing in hardware architecture, silicon implementation, and AI acceleration.

Tell us about your company?

RaiderChip is a European fabless semiconductor company founded in 2024, developing a proprietary NPU architecture to bring Generative AI directly to edge devices.

Our business model combines the development of semiconductor chips with licensing our NPU architecture as intellectual property (IP) for integration into third-party SoCs.

What problems are you solving?

Deploying Generative AI at the edge presents two fundamental challenges: achieving high energy efficiency under strict power and thermal constraints, while retaining the flexibility to support rapidly evolving models and architectures.

General-purpose processors offer flexibility but lack the energy efficiency required for these workloads. Conversely, conventional NPUs are more efficient but often struggle to support new Generative AI architectures, resulting in limited model ecosystems, conversion requirements, and precision constraints that may compromise model capabilities.

RaiderChip addresses these challenges with a flexible, energy-efficient architecture purpose-built for Transformer inference at the edge.

What application areas are your strongest?

Our technology is particularly well suited to robotics, automotive, and industrial automation, where AI must interact directly with the physical world under strict power, latency, and autonomy constraints. These are precisely the sectors driving the transition towards Physical AI.

Nevertheless, we believe Generative AI has the potential to become a general-purpose technology, with applications across virtually every sector of the economy. That is why we have developed a scalable architecture that can be tailored to the performance, power, and cost requirements of a wide range of devices and applications.

What keeps your customers up at night?

For companies building edge products, one of the biggest challenges is integrating a technology as disruptive as Generative AI into their own businesses and applications, for which established technology roadmaps do not yet exist. As AI models evolve rapidly, they must decide today which performance levels, models, and architectures their products will need to support throughout their lifecycle.

Another major concern is technological sovereignty and strategic dependence on a small number of international suppliers of advanced technologies. Recent geopolitical tensions and export restrictions on advanced hardware have highlighted how this concentration can jeopardize business autonomy and continuity, as well as the ability to adapt and remain competitive.

What does the competitive landscape look like and how do you differentiate?

The industry has yet to fully resolve the fundamental trade-off between flexibility and energy efficiency in Generative AI processing. RaiderChip addresses this challenge with an architecture that delivers the efficiency of dedicated hardware and the flexibility to support new models without redesigning the silicon.

The key to our flexibility and efficiency lies in specialized hardware kernels that cover all fundamental Transformer operations. Inference runs through a hardware pipeline with deterministic latency. Firmware defines an optimized, model-specific execution strategy in advance, while a hardware scheduler distributes operations across tensor, vector, and memory units. This keeps those units highly utilized, maximizing performance and energy efficiency.

This allows us to optimize execution model by model, maximizing performance and achieving the advantages of an almost custom-designed architecture while retaining the flexibility to support new architectures without redesigning the silicon.

Furthermore, by executing supported Generative AI workloads entirely on a single NPU, we avoid splitting their processing across CPUs, GPUs, and other accelerators, reducing unnecessary data transfers, bottlenecks, and integration complexity. Combined with high resource utilization, this avoids unnecessary hardware overprovisioning and enables more efficient designs in terms of both power consumption and silicon area, improving cost competitiveness.

What new features/technology are you working on?

We believe the future of Physical AI lies in combining multiple specialized models working together. This requires two fundamental capabilities: native support for models specialized through fine-tuning and post-training, and concurrent execution of multiple Generative AI models. Our architecture already supports both capabilities.

The first is particularly important for bringing Physical AI into industrial applications, where models must be specialized for each application. Through fine-tuning and post-training, customers can adapt foundation models using their domain knowledge and proprietary data, and run these specialized versions natively on our NPU.

The importance of concurrent execution is clearly illustrated by our recent Robotics demonstration (https://www.youtube.com/watch?v=dzRwKQdZvKA). In this demonstration, we bring cognitive capabilities to robotic control by replacing joystick-based operation with natural language instructions. The robots and their physics are simulated in MuJoCo, Google DeepMind’s physics simulator, where robot makers train their AI policies; the intelligence runs on real hardware, the Kairós FPGA-based NPU prototype. A speech recognition model transcribes the instructions, a four-billion-parameter reasoning model interprets the objectives and plans the movements as a timed sequence of velocities, and robotic control policies execute them. All ten models, including speech recognition, reasoning, and robotic control policies, are resident and execute concurrently on a single NPU, locally and in real time, without any cloud connection.

How do customers normally engage with your company?

We are currently moving towards the tape-out of Kairós, our first-generation chip.

In the meantime, we engage with companies from the earliest stages of technology evaluation, offering demonstrations on our FPGA-based NPU prototype, which supports more than 50 models and is available for evaluation under a non-disclosure agreement.

In parallel, RaiderChip offers its NPU architecture as licensable intellectual property (IP) for integration into third-party SoCs. Our modular and scalable architecture allows hardware resources to be tailored to the requirements of each application, optimizing performance, power consumption, and silicon area.

This approach enables semiconductor companies to add Generative AI to their own SoCs, tailored to the requirements of their target applications and optimized for cost.

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