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The Biggest Private EDA Company

The Biggest Private EDA Company
by Paul McLellan on 10-21-2013 at 5:02 pm

I talked this morning with fellow Brit David Halliday. More importantly, he is CEO of Silvaco, which he thinks must be the biggest private EDA company in the world. He didn’t reveal their revenue numbers but they have around 250-300 people and are profitable so you can make your own estimate.

David became CEO when Ivan Pesic,… Read More


Analog & Mixed-Signal Design Lunch & Learn

Analog & Mixed-Signal Design Lunch & Learn
by Daniel Nenni on 10-20-2013 at 9:00 pm

I’m a big fan of lunch and learns, mainly because I’m a big fan of lunch but I also like to learn. I’m also a big fan of Tanner EDA which is why I helped organize this event. Face to face interaction amongst the fabless semiconductor ecosystem is critical to our success so stop on by and network, lunch is on me.

Take a look at the Brief HistoryRead More


Server Shift to ARM Becomes a Stampede

Server Shift to ARM Becomes a Stampede
by Paul McLellan on 10-19-2013 at 3:00 pm

I have been at the Linley Microprocessor Conference today. This is the one that is not about mobile: about servers, networking, base-stations. Probably the most important story about the whole industry is that the “shift to ARM becomes a stampede.”


In this market it seems to be driven by the 64-bit ARMv8 instruction… Read More


GSA Memory+ Conference in Taiwan

GSA Memory+ Conference in Taiwan
by Paul McLellan on 10-18-2013 at 3:02 pm

The GSA Memory+ conference Taiwan will take place on (Halloween!) October 31, 2013 at the Regent Taipei, Taiwan. The main theme of this year is highlighting Memory—the Critical Enabler for Prominent and Emerging Applications in System Logic Solutions.

GSA Memory+ Conference is the global industry event dedicated to all memory… Read More


New at DAC: IP, Automotive, Security

New at DAC: IP, Automotive, Security
by Paul McLellan on 10-18-2013 at 12:09 pm

The deadline for panel sessions, workshops, tutorials and co-located conferences for DAC 2014 is October 21st. That’s next Monday!

DAC 2014 will not only focus on EDA and embedded systems and software but
also include:

  • design methods for automotive systems and software
  • hardware and embedded systems security
  • IP (semiconductor
Read More

CEVA-XC Wireless Baseband Core

CEVA-XC Wireless Baseband Core
by Paul McLellan on 10-17-2013 at 5:51 pm

Eyal Bergman of CEVA announced their latest core yesterday at the Linley Microprocessor Conference. It’s their 4th generation CEVA-XC solution, which is the core of their offering for wireless baseband. It builds on 3 previous generations of CEVA-XC’s that were mainly targeted toward handset applications. This… Read More


TSMC Continues To Fire On All Cylinders

TSMC Continues To Fire On All Cylinders
by Ashraf Eassa on 10-17-2013 at 5:03 pm

Taiwan Semiconductor Manufacturing Corporation is the world’s leading semiconductor foundry by revenue and, by extension, profitability. While I am deeply saddened that current CEO Morris Chang will be retiring (again) shortly, I am hopeful that his successor will be able to continue the legacy of foundry industry leadership… Read More


Putting the Ten in Tensilica

Putting the Ten in Tensilica
by Paul McLellan on 10-17-2013 at 3:55 pm

Chris Rowen of Cadence’s Tensilica announced the tenth generation of the Xtensa customizable processor at the Linley Microprocessor Conference yesterday. Chris was one of the founders of Tensilica…back in 1997. I believe that the first version was released in 1999. Over the years the Tensilica business changed.… Read More


Semiconductor IP Library QA Just Got Easier

Semiconductor IP Library QA Just Got Easier
by Daniel Payne on 10-17-2013 at 12:05 pm

Imagine that you’re working in a CAD group and just received a new library of a few hundred IP blocks and you needed to know if these blocks conform to your design and quality standards. There are many questions about library and IP quality:

  • Are all of the views consistent (layout, schematic, HDL, test, timing, SPICE)?
  • Are there
Read More

How to Simplify Complexities in Power Verification?

How to Simplify Complexities in Power Verification?
by Pawan Fangaria on 10-17-2013 at 11:00 am

With multiple functionalities added into a single chip, be it a SoC or an ASIC, maintaining low power consumption has become critical for any design. Various techniques at the technology as well as design level are employed to accomplish the low power target. These include thinner oxides in transistors, different sections of … Read More