This comparison of smartphone processors from different companies and fab processes was originally going to be a post, but with the growing information content, I had to put it into an article. Here, due to information availability, Apple, Huawei, and Samsung Exynos processors will get the most coverage, but a few Qualcomm Snapdragon





Making Full Memory IP Robust During Design
Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More
CEO Interview: Charlie Janac of Arteris IP
Charlie Janac is president and CEO of Arteris IP where he is responsible for growing and establishing a strong global presence for the company that is pioneering the concept of NoC technology. Charlie’s career spans over 20 years and multiple industries including electronic design automation, semiconductor capital equipment,… Read More
Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II
The semiconductor industry growth is increasing exponentially with high speed circuits, low power design requirements because of updated and new technology like IOT, Networking chips, AI, Robotics etc.
In lower technology nodes the timing closure becomes a major challenge due to the increase in on-chip variation effect and… Read More
Quick Error Detection. Innovation in Verification
Can we detect bugs in post- and pre-silicon testing where we can drastically reduce latency between root-cause and effect? Quick error detection can. Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on novel research ideas. Feel free to comment.
The Innovation
This month’s pick is Logic Bug Detection… Read More
A Historical Case for Precision – or How a Gun Made in a Dungeon Changed the World
We take for granted today the staggering precision of modern technology. Cars, electronics, robots and medical equipment, all come off the factory floor composed of effortlessly interchangeable parts; but this was not always the case. In the late 18th century most things that required any kind of precision were made by hand, … Read More
Getting Physical to Improve Test – White Paper
One of the most significant and oft repeated trends in EDA is the use of information from layout to help drive other parts of the design flow. This has happened with simulation and synthesis among other things. Of course, we think of test as a physical operation, but test pattern generation and sorting have been netlist based operations.… Read More
Xilinx Moves from Internal Flow to Commercial Flow for IP Integration
I’ll never forget first learning about Xilinx when they got started back in 1984, because the concept of a Field Programmable Gate Array (FPGA) was so simple and elegant, it was rows and columns of logic gates that a designer could program to perform any logic function, then connect that logic to IO pads to drive other chips … Read More
Netlist CDC. Why You Need it and How You do it.
The most obvious question here is “why do I need netlist CDC?” A lot of what you’re looking for in CDC analysis is really complex behaviors, like handshakes between different clock domains, correct gray coding in synchronizing FIFOs, eliminating quasi-static signals and the like. Deeply functional, system-level intent stuff.… Read More
Semiconductors Not as Bad as Expected!
In the early stages of the global COVID-19 pandemic, most forecasters expected the semiconductor market to decline in 2020, including our May Semiconductor Intelligence projection of a 6% drop. However, the semiconductor market has shown surprising strength so far this year. WSTS reported the 2Q 2020 semiconductor market … Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet