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Roots of trust can’t prevent attacks through side-channels which monitor total power consumption or execution timing. Correcting weakness to such attacks requires pre-silicon vulnerability analysis. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO)… Read More
Back in 2020 I first learned from Synopsys about how they had engineered a better way to do optimize layouts on digital designs by using machine learning techniques, instead of relying upon manual approaches. The product was named DSO.ai, standing for Design Space Optimization, and it produced a more optimal floor-plan in less… Read More
One of the career Intel employees (33+ years) that Pat Gelsinger brought back is Stuart Pann. Stuart is now the Senior Vice President of the Intel Corporate Planning Group. He does not have direct foundry experience but he certainly knows Intel and Pat so it will be interesting to see where this goes.
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Humans certainly have always had an aesthetic preference for symmetry. We also see symmetry showing up frequently in nature. The importance of symmetry in electronic designs has been apparent for decades. There are a host of analog structures that require balanced layout. For instance, these include differential pairs and … Read More
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U.S. President Joe Biden served notice on the automotive industry that he expects auto makers to shift 50% of vehicle sales to those with electric power trains by 2030. Of course, he included plug-in hybrids in the mix – perhaps in deference to Toyota – and Tesla was oddly absent from the announcement made on the South… Read More
Dan and Mike are joined by Michael Munsey, senior vice president of marketing, business development and corporate strategy at Perforce. Michael discusses the unique IP management requirements of early stage semiconductor companies and how to address these requirements. The risks associated with a sub-optimal approach are… Read More
At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet