Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

The language is new, but the motivation is familiar to anyone who has worked in chip design.

Design complexity keeps increasing. The number of tools in the flow keeps increasing. Logs, reports, waveforms, constraints, schematics, layouts, and verification artifacts keep multiplying. Meanwhile, engineering expertise remains the bottleneck. Analog and mixed-signal design feel this even more sharply than digital because so much of the work depends on topology intuition, device-level tradeoffs, layout sensitivity, and a long sequence of judgment-heavy iterations.

The recent announcements from Cadence, Siemens EDA, and Synopsys therefore matter. They are not simply another generation of AI assistants. They signal an architectural shift: from AI as a helper sitting beside EDA tools toward AI as an orchestration layer that can plan, call tools, interpret results, and iterate.

At the same time, I think we should be careful about what problem has actually been solved.

The current wave is impressive, but it is not yet the same as a persistent, learning, correctness-aware analog design intelligence system. Most public material still points to systems that are strong at workflow orchestration and tool invocation, but less explicit about deep graph-native circuit reasoning, long-horizon design memory, cross-design learning, and correctness propagation inside the optimization loop.

This distinction matters. Teaching an AI system to run an engineering workflow is not the same thing as teaching it to accumulate engineering judgment. For analog design especially, that judgment is learned not only from design artifacts, but from the sequence of decisions, experiments, failures, and recoveries that produced them.

This post is my attempt to place the current state of the art on a few technical dimensions — especially from the perspective of analog and custom design, and then outline the research directions that seem most promising.

Chatbots and beyond

A good place to start is by recognizing what these systems are not. They are not simply LLM wrappers. Cadence’s AgentStack and AI Super Agents, Siemens EDA’s Fuse EDA AI Agent, and Synopsys’ AgentEngineer all point toward a common direction: AI systems that can decompose engineering goals into tool-grounded actions, coordinate workflows across multiple stages of the design process, interpret results, and iterate toward objectives.

The details differ, but the underlying architectural shift is remarkably consistent. Across all three vendors, the center of gravity is moving from “AI answers a question” toward “AI coordinates engineering work”.

That is, unmistakably, a major step forward. The more interesting question, however, is whether workflow coordination is the endpoint — or merely the foundation for something deeper.

To answer that question, it helps to examine today’s agentic EDA systems along a few dimensions that, in my view, distinguish workflow automation from genuine design intelligence.

Dimension 1: Flow Coverage

The strongest public claims today are around flow orchestration.

Cadence presents one of the clearest decompositions: ChipStack for RTL design and verification, ViraStack for analog design and verification, and InnoStack for implementation and signoff. Siemens positions Fuse across a broad engineering landscape spanning architecture, custom IC, verification, physical implementation, manufacturing, and PCB workflows. Synopsys similarly describes agent collaboration across RTL generation, verification, planning, and engineering automation.

On the flow-coverage dimension, the industry has clearly crossed a critical threshold. The ambition is no longer isolated sizing, isolated testbench generation, or isolated log triage. The ambition is full-flow coordination.

But broad flow coverage is not the same thing as deep design cognition.

For digital implementation, much of the state already exists in formalized artifacts: RTL, constraints, timing graphs, floorplans, and signoff reports.

For analog design, the most significant state often lives somewhere else. It lives in the designer’s understanding of:

• why a topology was chosen
• why a device was biased that way
• which failure mode is suspected
• which tradeoffs have already been explored
• which paths were abandoned weeks ago

Automating analog flow steps is valuable. But analog expertise is accumulated through successive design iterations, not isolated tool executions. Externalizing and ultimately compounding that design cognition is a much harder problem.

Dimension 2: Memory and Design Context

This is where the public systems start to diverge.

Cadence’s Mental Model concept is particularly interesting because it recognizes that agents need structured representations of design intent rather than relying entirely on prompt context. Siemens discusses RAG, EDA-specific parsers, Agent Skills, and executable playbooks. Synopsys emphasizes systems that learn and improve through feedback. All of these are important developments. The key question, however, is whether these architectures are primarily contextual, or whether they actually learn from design evolution.

Contextual memory answers questions such as:

• What is the current design?
• What is the current specification?
• What simulation result did we just obtain?
• What existing IP looks similar?

Evolutionary memory answers a different set of questions:

• What did we try?
• Why did we try it?
• What changed?
• Which metrics improved?
• Which metrics regressed?
• Which failure modes repeated?
• Which designer overrides proved correct?
• Which fixes consistently worked across designs?

For analog design, the second category is often more consequential than the first. A design is not merely a netlist plus constraints. It is the outcome of a trajectory through a high-dimensional tradeoff space — a sequence of hypotheses, design decisions, simulations, failures, corrections, and refinements. Preserving that trajectory may ultimately be more valuable than preserving the final artifact alone.

I find the concept of a Design Evolution Graph particularly compelling. Every iteration becomes a transition: ‘State Sₙ → Action → State Sₙ₊₁’ with measurable deltas in performance, correctness, yield, power, area, robustness, and physical feasibility. Over time, those transitions become the raw material for a reusable Pattern Library of failure modes, fixes, tradeoffs, and convergence strategies. Without explicit evolution memory, an agent may become highly effective within a single session while still failing to accumulate knowledge across months, projects, and topology families.

If Design Evolution Graphs capture how a design changes over time, the next question is whether an AI system truly understands what it is changing.

Dimension 3: Reasoning Over Analog Structure

The public vendor systems appear strongest where they can ground LLM behavior in tools, skills, and structured context.

That grounding is necessary, but for analog design, I do not think it is sufficient. Analog circuits are inherently graph-structured. Devices connect through nets, signal paths interact with bias networks, feedback loops determine stability, matching groups influence yield, and layout structures introduce parasitic effects. Many of the most important engineering conclusions emerge from these relationships rather than from any individual artifact.

Consider a simple phase-margin failure.

A workflow-oriented agent may read the report, identify low phase margin, invoke an optimization flow, rerun simulations and report the outcome

A circuit-intelligent system would ideally reason at a deeper level. It would understand the compensation topology, the loop structure, device operating regions, extracted parasitic evolution, previous compensation attempts, similar convergence trajectories from past designs, and the likelihood that a proposed fix simply repeats a previously unsuccessful strategy.

Instead of saying “Phase margin is low.”, it might conclude that “Increasing the compensation capacitance is unlikely to improve phase margin further. The last three optimization iterations already achieved the intended shift in the dominant pole, yet stability improved only marginally. The remaining degradation appears more consistent with layout-induced parasitic loading around node X than with insufficient compensation.”

That is a fundamentally different level of reasoning. And this is where a pure ‘LLM plus Tool skills’ architecture starts to feel incomplete. A deeper analog intelligence layer likely requires graph-native representations, topology-aware retrieval, temporal state reasoning, constraint propagation, and some form of neural-symbolic inference operating directly on circuit structure.

In other words, the system should not merely understand reports. It should understand circuits.

Dimension 4: Correctness and Trust

All serious EDA agent systems recognize that correctness cannot be delegated to a language model. Public materials consistently emphasize guardrails, validation, auditability, human oversight, and deterministic EDA tools. That is the right posture.

But there is still an important distinction between correctness-aware execution and correctness-aware planning. Today, verification is often downstream. The agent proposes an action and deterministic tools validate it afterward. That is significantly better than unconstrained generation, but correctness remains largely reactive.

For analog systems, correctness should increasingly become part of planning itself. One useful mental model could be a three-tier correctness loop:

Tier 1: Symbolic legality checks before an action is allowed.

Tier 2: Inexpensive physics-based sanity checks on every accepted step.

Tier 3: Expensive verification gates such as corners, Monte Carlo, DRC, LVS, PEX, reliability, and post-layout simulation.

The goal is not simply to discover failure after exploration, but to avoid entering known-bad regions of the design space in the first place.

In analog design, that distinction matters because invalid exploration can consume enormous simulation resources while generating little useful information. Correctness-aware planning is not merely a safety feature — it is an efficiency feature.

Dimension 5: Simulation Efficiency

One dimension that receives less attention than it deserves is simulation efficiency.

Ultimately, analog design productivity is not measured by how many agent actions occur. It is measured by how quickly designs converge.

Many analog bottlenecks are really simulation bottlenecks:

• Corner sweeps
• Monte Carlo runs
• Post-layout validation
• Reliability analysis

An agent that requires thousands of exploratory simulations may appear intelligent while actually increasing engineering cost. A truly effective analog design intelligence system should reduce the number of simulations per design closure, invalid design evaluations, redundant exploration, unnecessary corner execution, and repeated failure patterns.

This is where memory, graph reasoning, and correctness-aware planning become economically critical. If an agent remembers which classes of actions repeatedly failed, understands which topologies behave similarly, and can predict which regions of the design space are unlikely to converge, it can allocate simulation budgets far more efficiently.

In analog design, the ultimate measure of intelligence may not be better answers — it may be fewer simulations required to reach a trustworthy design.

Dimension 6: Deployment and Enterprise Reality

Enterprise deployment remains critically important. Semiconductor companies operate in environments where:

• IP is highly sensitive
• flows are heavily customized
• toolchains are heterogeneous, and
• methodology knowledge has accumulated over decades

In publicly available material, Siemens seems to be particularly explicit about air-gapped deployment, local infrastructure, governance, auditability, and multi-tool integration. Cadence and Synopsys naturally emphasize deep integration within their own ecosystems, which offers clear advantages in performance, reliability, and methodology awareness.

Yet a strategic tension remains. The more deeply intelligence is embedded within a single tool stack, the more powerful it can become inside that environment. At the same time, the harder it may become to transfer knowledge across mixed toolchains, internal scripts, foundry-specific methodologies, and customized engineering workflows.

For analog design, this challenge is especially significant because real organizations rarely operate within perfectly homogeneous environments.

So Where Are We Today?

My current assessment is that the state of the art has reached strong agentic workflow orchestration, particularly when agents are tightly integrated with mature EDA tools.

The strongest current capabilities appear to be:

• multi-agent flow orchestration
• spec-to-artifact generation in selected domains
• tool invocation and report interpretation
• regression and debug assistance
• design-space exploration using existing engines
• enterprise workflow integration
• emerging mental-model representations, and
• increasingly mature deployment models

At the same time, most current systems appear to assume that design state can largely be represented as contextual knowledge, validation can remain mostly tool-mediated, and workflow decomposition is the dominant bottleneck. This leads to strategies where playbooks are expected to encode most required expertise, session context plus retrieval is sufficient, and intelligence can remain largely localized within vendor ecosystems.

These assumptions are understandable. They reduce complexity, accelerate deployment, and leverage the enormous strengths of existing EDA infrastructures. However, they also define the limits of first-generation systems.

And where do we go from here?

The most compelling future direction, in my view, is not a larger language model. It is a persistent analog design intelligence system built around four foundational ideas.

1. Graph-Native Design State

Represent devices, nets, hierarchy, constraints, layout regions, simulation results, verification artifacts, metrics, agent actions, and failures as a heterogeneous temporal property graph.

The graph should support reasoning about any historical design state, not just the current one.

2. Separation of State and Evolution

The current design and the history that produced it should coexist but remain logically distinct.

The State Plane answers: “What is the design now?”, while the Evolution Plane answers: “How did it get here?”.

This distinction enables replay, rollback, learning, auditing, and pattern mining.

3. Learning from Design Trajectories

Every iteration should generate something akin to a reusable record, say (state, action, next_state, metric_delta, provenance)

Over time, these trajectories become a source of transferable engineering knowledge spanning designs, teams, and topology families.

4. A Composed Reasoning Kernel

Symbolic systems should own hard constraints. Graph reasoning systems should own structural inference and topology retrieval. Language models should own planning, explanation, and interaction.

Essentially, the LLM should be a component of the system, not the trust boundary.

Together, these ideas point toward AI systems that do more than automate engineering workflows — they accumulate engineering judgment.

Closing Thoughts

The ideas outlined above are, of course, only a starting point. Many research questions remain, and I suspect they will define much of the next decade of innovation in agentic analog EDA.

The current generation of agentic EDA systems represents solid progress. Cadence, Siemens EDA, and Synopsys are all moving toward a future where AI systems coordinate multi-step engineering work rather than simply answer questions. That is an important inflection point.

For analog design, however, the next leap will require something fundamentally different. AI must learn not only from specifications, reports, layouts, and prompts, but from the design trajectories that connect them — the decisions made, alternatives explored, failures encountered, and corrections that ultimately produced a successful design.

Persistent design memory, explicit evolution tracking, graph-native reasoning, correctness-aware planning, simulation-efficient exploration, and cross-design learning are all pieces of that broader vision.

The first generation of agentic EDA systems is teaching machines how to operate engineering tools. The next generation must teach them how engineering judgment itself evolves. For analog design, learning from design trajectories — not just design artifacts, may ultimately define the difference between workflow automation and genuine design intelligence.

By Chandra Manglani

Also Read:

Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test

Applying QED to Hardware Accelerator Verification. Innovation in Verification

From Tokens to Infrastructure: Why Compute, Memory, and Power Will Determine the Future of AI

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