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PowerArtist RTL Power Estimation Folds into KeysightBack in the late 1990s, Sente launched a…Read More
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A tower-like heterogeneous packaging architecture for the AI era VEMC: The Vertical System…Read More
This past week we … Read More
Unreachability (UNR) analysis, finding and definitively proving that certain states in a design cannot possibly be covered in testing, should be a wildly popular component in all verification plans. When the coverage needle stubbornly refuses to move, where should you focus testing creativity while avoiding provably untestable… Read More
Regardless of where you grew up you probably know the story of Alice in Wonderland. The story is over 100 years old, but holds up to the present day, thanks in part to some magic from Disney. It evokes visions of a place that elicits admiration and wonder, to create a place of magical charm. In the context of AI, it takes on a more relevant… Read More
In the ever-evolving world of Conversational AI and Automatic Speech Recognition (ASR), an upcoming LinkedIn Live webinar is set to redefine the speech-to-text industry. Achronix Semiconductor Corporation is teaming up with Myrtle.ai to bring you a webinar on October 24, 2023, at 8:30am PST.
Moderated by EE Times’ Sr. Reporter,… Read More
By Philippe Flatresse, Bich-Yen Nguyen, Rainer Lutz of SOITEC
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Eng. Islam Nashaat received his B.Sc. and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2010 and 2017, respectively. He joined Si-Vision as an Analog Physical Design Engineer in 2010, where he initiated the company’s CAD team in 2013, and became CAD and Physical Design Team Lead in 2016 after the company’s flagship … Read More
TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched. Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More
Synopsys recently hosted a cross-industry panel on the state of multi-die systems which I found interesting not least for its relevance to the rapid acceleration in AI-centric hardware. More on that below. Panelists, all with significant roles in multi-die systems, were Shekhar Kapoor (Senior Director of Product Management,… Read More
You are probably familiar with the acronym PPA, which stands for Power/Performance/Area. Sometimes it is PPAC, where C is for cost, since there is more to cost than just area. For example, did you know that adding an additional metal layer to a chip dramatically increases the cost, sometimes by millions of dollars? It requires a … Read More
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Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs