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Semiconductor Expert Forum

EP161: The Backstory of sureCore’s Ultra-Low Power Memories with Paul Wells

EP161: The Backstory of sureCore’s Ultra-Low Power Memories with Paul Wells
by Daniel Nenni on 05-12-2023 at 10:00 am
Categories: Uncategorized

Dan is joined by Paul Wells, CEO of sureCore. Paul has worked in the semiconductor industry for over 25 years. His experience includes Director of Engineering for Pace Networks where he led a product development team creating broadcast quality video & data silicon. He worked for Jennic Ltd as VP of Operations successfully … Read More

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Chip War without Soldiers

Chip War without Soldiers
by Sivakumar PR on 05-12-2023 at 6:00 am
Categories: Chiplet, Maven Silicon, Semiconductor Services
8 Comments

Semiwiki Creative Final

Every country realizes the importance of producing skilled chip designers who could decide their success as soldiers by creating advanced AI chips for winning the Chip War. Also, every country is now gearing up to build a good semiconductor manufacturing ecosystem to balance the global semiconductor supply chain that could … Read More

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SEMI ESD Alliance CEO Outlook Sponsored by Keysight Promises Industry Perspectives, Insights

SEMI ESD Alliance CEO Outlook Sponsored by Keysight Promises Industry Perspectives, Insights
by Bob Smith on 05-11-2023 at 10:00 am
Categories: Ansys, Inc., ESD Alliance, Events, IC Manage, Keysight EDA, Semiconductor Services, Siemens EDA

ESDA CEO Outlook

Spring wouldn’t be the same without an opportunity to hear from some of the most visible executives of electronic system design (ESD) market segment. The in-person CEO Outlook sponsored by Keysight and hosted by the ESD Alliance, a SEMI Technology Community, will be held Thursday, May 18, in Santa Clara, Calif.

Attendees can expect… Read More

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Takeaways from CadenceLIVE 2023

Takeaways from CadenceLIVE 2023
by Bernard Murphy on 05-11-2023 at 6:00 am
Categories: AI, Cadence, EDA

Takeways image

Given popular fascination it seems impossible these days to talk about anything other than AI. At CadenceLIVE, it was refreshing to be reminded that the foundational methods on which designs of any type remain and will always be dominated in all aspects of engineering by deep, precise, and scalable math, physics, computer science… Read More

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Alchip is Golden, Keeps Breaking Records on Multiple KPIs

Alchip is Golden, Keeps Breaking Records on Multiple KPIs
by Kalar Rajendiran on 05-10-2023 at 10:00 am
Categories: Alchip, Semiconductor Services

Alchip Revenue Breakdown along Nodes and Applications

I don’t know the story behind the name Alchip. I’ve been asking this question ever since its founding in 2003 and still haven’t found the answer. Wikipedia sometimes provides insights and stories behind names of companies, products and services but I couldn’t find any regarding the name Alchip. One thing is for sure. After its consistent… Read More

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Silicon Catalyst and Arm announce $150,000 Silicon Startup Contest!

Silicon Catalyst and Arm announce $150,000 Silicon Startup Contest!
by Daniel Nenni on 05-10-2023 at 6:00 am
Categories: Arm, Events, Semiconductor Services, Silicon Catalyst

Silicon Catalyst Arm contest 400x400

As I sift through mounds of semiconductor press releases trying to figure out the relevance (with mixed results) I consider it a learning experience even when they don’t really tell me anything. This one however tells me two very important things:

1) Arm is a much more competitive company with the new leadership. I saw a noticeable… Read More

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Curvilinear Mask Patterning for Maximizing Lithography Capability

Curvilinear Mask Patterning for Maximizing Lithography Capability
by Fred Chen on 05-09-2023 at 10:00 am
Categories: EDA, Lithography, Synopsys

Curvilinear 1

Masks have always been an essential part of the lithography process in the semiconductor industry. With the smallest printed features already being subwavelength for both DUV and EUV cases at the bleeding edge, mask patterns play a more crucial role than ever. Moreover, in the case of EUV lithography, throughput is a concern, … Read More

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Is Your Interconnect Strategy Scalable?

Is Your Interconnect Strategy Scalable?
by Bernard Murphy on 05-09-2023 at 6:00 am
Categories: AI, Arteris, IP

Design min

“Strategy” is a word sometimes used loosely to lend an aura of visionary thinking, but in this context, it has a very concrete meaning. Without a strategy, you may be stuck with decisions you made on a first-generation design when implementing follow-on designs. Or face major rework to correct for issues you hadn’t foreseen. Making… Read More

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Reconfigurable DSP and AI IP arrives in next-gen InferX

Reconfigurable DSP and AI IP arrives in next-gen InferX
by Don Dingee on 05-08-2023 at 10:00 am
Categories: eFPGA, Flex Logix, IP

InferX 2.5 reconfigurable DSP and AI IP from Flex Logix

DSP and AI are generally considered separate disciplines with different application solutions. In their early stages (before programmable processors), DSP implementations were discrete, built around a digital multiplier-accumulator (MAC). AI inference implementations also build on a MAC as their primitive. If the interconnect… Read More

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Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Tessent SSN Enables Significant Test Time Savings for SoC ATPG
by Kalar Rajendiran on 05-08-2023 at 6:00 am
Categories: EDA, Siemens EDA

Pattern Generation Block Level ATPG Flow

SoC test challenges arise due to the complexity and diversity of the functional blocks integrated into the chip. As SoCs become more complex, it becomes increasingly difficult to access all of the functional blocks within the chip for testing. SoCs also can contain billions of transistors, making it extremely time-consuming… Read More