TSMC’s AI Design Kit: Bringing Agentic AI Into Chip DesignTSMC is introducing an AI Design Kit, or…Read More
OpenAI and Synopsys Announce GPT-Synopsys: Why AI-Powered Chip Design MattersWow, OpenAI and Synopsys just announced a multiyear…Read More
Why the energy sector must plan for post-quantum cyber security nowIn a September 2026 World Economic Forum article,…Read More
TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and EcosystemsI spent a significant part of my career…Read More
The Pivotal Moments That Gave Rise to Silicon ValleyThe little-known decisions and breakthroughs—and the remarkable role…Read More
As I have been watching the developments in EDA and Semiconductor industry, it is apparent that we remain fragmented unless pushed to adopt a common standard mostly due to business reasons. Foundries are dictating on the rules to be followed by designs, thereby EDA tools incorporating them. Also, design companies needed to work… Read More
Now that the dominant approach to building an SoC is to get IP from a number of sources and assemble it into a chip, the issue of IP quality is more and more critical. A chip won’t work if the IP doesn’t work, but it is quite difficult to verify this because the SoC design team is not intimately familiar with the IP blocks since… Read More
Last May, Atrenta and TSMC announced the Soft-IP Alliance Program which uses SpyGlass and a subset of its GuideWare reference methodology to implement TSMC’s IP quality assessment program. TSMC requires all soft-IP providers to reach a minimum level of completeness before their IP is listed on TSMC online. Since TSMC … Read More
The first version of the debug platform Verdi (then called Debussy) dates back to 1996 over 15 years ago. The second version was released in 2002. And now SpringSoft is releasing the 3rd version Verdi[SUP]3[/SUP]which is a completely new generation. A tool environment like Verdi seems to need to be completely refreshed about every… Read More
Yield, no topic is more important to the semiconductor ecosystem. After spending a significant part of my career on Design for Manufacturability (DFM) and Design for Yield (DFY), I’m seriously offended when semiconductor professionals make false and misleading statements that negatively affects the industry that … Read More
July 16-19, 2012, Monte Carlo Resort, Las Vegas , Nevada , USA
ERSA-News: ERSA-NEWS ERSA’12 Website: http://ersaconf.org/ersa12
New embedded computing standards always take a while to get traction, and a burning question for innovators is what to do in the period between concept and acceptance. Sometimes, new ideas come when commercial silicon changes direction.… Read More
This year’s CEO forecast panel was held at Silicon Valley Bank. Bankers live better than verification engineers, as if you didn’t know, based on the quality of the wine they were serving compared to DVCon.
This year the panelists were Ed Cheng from Gradient, Lip-Bu, Aart and Wally (and if you don’t know who they… Read More
Every so often I come across a new company in EDA or one of its neighboring domains, new to me anyway, and new to SemiWiki. One such company is RunTime Design Automation (RTDA). They provide a suite of tools for managing server farms (or internal clouds which seems to be the trendy buzzword du jour). Running a few EDA scripts on a few servers… Read More
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Intel Foundry: AI performance now depends on the whole system