Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints – through full-chip sign-off.
The role includes supporting design verification and backend to tape out of the full chip and supporting full chip integration and full chip related tasks – STA, verification and power analysis.
- BSEE is required, MSEE is preferred.
- 5 and more years of experience in logic design using Verilog.
- Experience with architecture, specs, documentation, coding in Verilog and debugging.
- Knowledge of SoC, USB, DDR3/DDR4/MIPI and modem PHY designs – advantage.