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Xilinx in an ARM-fueled post-Altera world

Xilinx in an ARM-fueled post-Altera world
by Don Dingee on 06-29-2015 at 5:30 pm

When the news broke about the on, off, and on-again Intel-Altera merger a few weeks ago, I checked off another box on my Six Degrees of Kevin Bacon scorecard. That plus a $5 bill gets me a Happy Meal at McDonalds, but in a post-Altera world, it might be worth more.

On January 16, 2008, I’m sitting in a meeting with some Intel strategic marketing types discussing the embedded market. It’s a brain-picking session with Intel asking open-ended questions about trends and the competitive landscape – no NDA, because Intel isn’t sharing their information. I casually mention the concept of “SoC reconfigurability”, the idea of an FPGA sitting next to a processor core to accelerate the last inch of I/O. Lots of looking at each other and writing notes, not a lot of response, and no detailed architectural follow-up questions.

Maybe I just affirmed something Intel was already thinking about, or even working on. Maybe I planted the seed. I’ll never know. I do know that two and a half years later, that same group of Intel previews “Stellarton” at IDF 2010, a 45nm Atom E600 processor loosely packaged together with an undisclosed Altera FPGA. It’s in a huge multichip can, 37.5×37.5mm and 1466 pins, with only a couple choices of core speeds.

On March 1, 2011, Xilinx introduces the Zynq-7000 family. They grabbed an actual embedded core, the ARM Cortex-A9, and tightly integrated two of them (the processor system, PS) with a 28nm programmable logic (PL) fabric including a cache-coherent port between the PL and PS. The logic is either Artix-7 or Kintex-7 equivalent, ranging from 28K to 444K logic cells. The smallest version is in a 225-pin, 13x13mm BGA, and the biggest in a 900-pin, 31x31mm package, covering a range of I/O options with several dual-core speeds.

Xilinx won that round, hands-down, with a combination of IP (ARM plus theirs), process (TSMC), architecture, and packaging, and we should mention Vivado software as well. Intel still hasn’t figured out integration and small packages, even with the Quark core. Altera has responded with several well thought out ARM-based SoC offerings but hasn’t come close to the popularity of Zynq yet, partly due to the availability of maker modules like the Avnet ZedBoard family and Adapteva Parallela, and partly due to being behind on process.

To fix the behind-on-process-ness, Altera and Intel struck a foundry deal for 14nm FinFET in February 2013. FPGAs are a great way to prove out advanced nodes, makes sense. In March 2014, the agreement is extended to cover multi-die in system-in-package. A few months later, Intel starts talking about Xeon parts like Knights Landing with FPGA acceleration on chip, but doesn’t name Altera. The target is the new, “workload-optimized” server processor.

SemiWiki readers know we’ve been writing about workload-optimized processors for some time. The question becomes why buy the cow when the milk is already in production? I wrote about a year ago saying Intel would just license the technology, not buy the company. So, why did Intel throw down an obscene 8.6x revenue multiple for Altera at $16.7B, when I speculated they wouldn’t pay 2x?

That’s what it took to keep Altera technology out of the hands of AMD, AppliedMicro, Broadcom, Cavium, and Qualcomm – all companies who understand low-power, tight SoC integration with spiffy 64-bit ARMv8 cores here or on the way. And, when Broadcom fell to Avago at a 4.4x revenue multiple for $37B at the end of May, the urgency for Intel went up. If Intel hopes to hold off the ARM hordes pounding at the data center door, this is one way to buy time. (But, there’s probably a catch. Altera has a lot of military business – they list 22% under industrial, military, and automotive. Prediction: Intel has to spin off a subsidiary to serve Altera’s defense biz before regulators approve the transaction.)

Meanwhile, Xilinx presses their advantage. By November 2013, their first UltraScale parts were ready in TSMC 20nm. In February 2015, they announce UltraScale+ in TSMC 16FF+, and begin talking about an upgrade for Zynq. Upgrade may be vastly understated on my part, because the Zynq UltraScale+ MPSoC is a complete redesign, with not one but three ARM IP blocks – the application processing unit with quad Cortex-A53 cores, the real-time processing unit with dual Cortex-R5 cores, and the graphics processing unit with a Mali-400 MP.

“That’s not exactly an embedded SoC.” And, you’d be correct, at least in full-up configurations. The smallest variant is a 484-pin, 19x19mm package, while the biggest one is a 1924-pin, 45x45mm with everything. Their product tables and selection guide tell the whole story. In fact, looking at the top of those tables, one can see the larger parts are targeting infrastructure.

On one side of the street, we have the new and improved Intel-Altera, maybe with a little piece of the defense biz carved out to satisfy the suits, targeting servers and the cloud.

On the other side of the street, we have the ARM-fueled chip companies with a lot to prove in servers, and customization and mobile or embedded SoC experience on their side.

Patrick Moorhead was quoted in Re/code saying FPGAs are good for two things: ASIC prototyping, and workload optimization as companions to server CPUs. He forgot one: building devices in low volumes where the requirements don’t justify the cost of ASIC customization. That is why Xilinx is big in defense and broadcast video circles – nasty processing requirements well suited for FPGA acceleration, but not a lot of systems built. The classic radar and image processing architecture has a high-data rate front end decimation done in FPGA, with a lower-data rate back end in a general-purpose CPU and software.

Of course, that can be two chips. A regular Xilinx Virtex UltraScale+ FPGA could certainly be connected to say, a Broadcom SoC with a Vulcan ARMv8 core. (Interesting take on Avago-Broadcom for servers in The Platform.) But, it’s two chips, and cache coherency for I/O is still a problem in some applications. Integration wins, for several reasons, if done right.

I thought it interesting that Moorhead tossed out two names as possible suitors for Xilinx: IBM, and Qualcomm. In a bigger picture view, IBM is a compelling alternative with OpenPower, and it would likely not mess up the rest of Xilinx’s business. Qualcomm has money, and buying Xilinx might buy them customers.

Other voices, particularly Steve Casselman and analyst Gus Richard, suggest that Xilinx should go on offense, acquiring AMD. That would put Xilinx squarely in an X86 play, removing some of the ARM server uncertainty, and might get exciting if GlobalFoundries gets involved. Casselman also points out that Xilinx has an advantage in run time and partial reconfiguration technology.

There are also cultural considerations. Intel may have learned from the Wind River acquisition, leaving them essentially alone as a subsidiary with their own brand. Altera may be run the same way, hopefully – because if not and Intel brings them in, there’ll be a lot of defectors at the end of the customary two-year retention agreement. Xilinx may not be a great cultural fit with some of these other SoC firms, either.

As our readers know, Xilinx owns the FPGA-based prototyping segment, and pretty much owns the embedded programmable SoC. It’s the embedded play that that is the wild card here. Lattice is still mostly in the logic-consolidation business. Microsemi plays well in some niches, particularly aerospace with extended temp range parts, but has nothing near the performance levels of Xilinx. Altera may or may not be able to hang in the embedded SoC business, depending on what Intel decides to do (or is forced to do by the feds).

And, there is still the FPGA programming “problem” in the data center context. Intel is trying to OpenCL their way out, with a manycore Xeon solution where FPGAs accelerate particular instructions. Xilinx embraced that in their SDAccel environment introduced at the end of 2014. Philosophically, designing and coding a server is going to undergo a huge transformation.

If this comes down to an Intel-Xilinx contest, it’s messy. On the one hand, Intel will have a hard time touching Xilinx on the embedded side, even if Altera is completely independent. On the other, sheer Intel weight in servers makes this a mismatch – infrastructure is home field advantage for them, and they will aggressively defend it. I don’t think Xilinx will fall into that trap, but most of the media is portraying it that way.

When all the ARM players are aligned – AMD, AppliedMicro, Avago, Cavium, Qualcomm, and Xilinx at the top of the list – what develops is an Apple vs. Android analogy that unfolded in smartphones. That may be exactly the model ARM is banking on, where no single vendor dominates, but the combined force of many vendors working in server space eventually matches up and perhaps overtakes Intel. ARM has to find the right message, however. Power consumption and die size don’t stand out the way they did in mobile. Customization is a better story.

I expect the low-volume play to continue unfolding. Xilinx will win with Zynq UltraScale+ MPSoC in somewhere like a big broadcast center, or an IoT hybrid cloud implementation, or some other thing that looks more like embedded than enterprise. Those type of SoC wins will add up to substantial numbers, and Xilinx will grow accordingly – on top of a stable base of traditional FPGA and embedded SoC business. Meanwhile, Qualcomm et al will be in experimentation mode, trying to find the right combination of features for a ARM-based networking infrastructure SoC. Intel-Altera will probably see wins in high-performance computing environments, perhaps running into IBM Watson in the cloud, and the jury is out on what happens to Altera’s traditional business.

I’m going to miss the Altera-Xilinx interplay, it just won’t be the same. Reality was there was no such thing as “an FPGA” – there were a lot of different programmable technologies, and they had to evolve to stay relevant. (We haven’t even touched on Achronix, or visited Tabula’s grave.)

Xilinx gets that everything has to work in unison, and that the real battleground isn’t foundries – important, but not the entire answer. Once size/power/cost/yield/reliability goals for a chip are in place, this comes down to scalability, integration, programming tools, and software support. Xilinx has the ability to compete in both embedded and data center applications. Casting them in only a foundry play or only a data center play misses the point.

Just as Avago-Broadcom changed the financial picture for Intel, things could change radically if Xilinx suddenly finds itself either buyer or seller. Which is a good place to open discussion: what are your thoughts on these observations, and what else might develop in this mix of opportunity?

Also Read: Why Did Intel Pay $15B For Altera?

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