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Xilinx UltraScale gives you 25% more packing than you know who…

Xilinx UltraScale gives you 25% more packing than you know who…
by Luke Miller on 08-27-2014 at 11:30 pm

Coke with no ice. You see I am not cheap, or even frugal but a good steward. One of the things that I hate the most is waste. You know lights on in every room, door open during winter and driving 25 miles to save a dollar on gas.

One will notice fairly quickly that with Xilinx UltraScale 20nm FPGAs coupled with the new-fangled analytical router that the Xilinx UltraScale FPGAs are very lean on waste. There is nothing more frustrating than to plan your FPGA design and only hit 50-60% full before one has timing and/or routing issues. Xilinx has a very good white paper just out that I would encourage you to read. It is wp455, ‘UltraScale Architecture: Highest Device Utilization, Performance, and Scalability’.

I will quickly note here, the paper mentions the ‘competition’. Now, I do not want to be presumptuous here, nor name names, so I will not mention that the competitor is Altera, which would not be prudent, after all it could be Achronix, right? But certainly not Altera. Shucks, who am I fooling, it is Altera.

A nice test case was run, both the Arria 10 (I assume) and UltraScale 20nm. Both used the SAME design code, from Open Cores and off you go. The results, as expected hammered the competition. See Below:

Before you get all spun up here, BOTH devices had about the same logic cell density of about 1160K cells. This is a blind test, all things equal. No griping please. UltraScale roughly was able to use 25% more resources than Altera. This a real deal, and a big deal. Do you like paying for resource you cannot use? No one does! The test also highlights the differences not only in Xilinx’s ability to route better but the architectural improvements that are superior to Altera. Xilinx rebuilt its router and pretty much their FPGAs.

The other highlight of the white paper comes in the form of scaling using Xilinx UltraScale. This means design migration from 20nm to 16nm. “For example, any UltraScale FPGA in a package ending D1924 is compatible with all other UltraScale FPGAs in D1924 packages. This strategy provides package footprint migration between Kintex UltraScale FPGAs and Virtex UltraScale FPGAs built on both 20 nm and 16 nm FinFET processes.” This is great as PBC rework is both costly and time consuming.

Rounding out this white paper 455, is the fact that Xilinx’s UltraScale has ASIC like clocking. This is key, not only in timing closure but the ability to pack fuller, tighter designs at a higher clock frequency. So you can use more of the Xilinx FPGA, and more cycles in the Xilinx FPGA. That is a double whammy. Speaking of which, remember that show with the whammies? Big bucks, no whammies stop… I will leave this blog on a very corny note; if you want no whammies in your design, then may I encourage you to read up on Xilinx, and make the wise choice for your next design, or even your current design, it may not be too late to switch, you truly will not regret it.

Also read:

Develop High Performance Machine Vision in the Blink of an Eye

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