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Silicon Measurement Data Gives Insights to Using Metal Fill With Inductors

Silicon Measurement Data Gives Insights to Using Metal Fill With Inductors
by Tom Simon on 08-27-2014 at 4:00 pm

Metal fill requirements for inductors are now a fact of life. Fill has long been seen as detrimental to device performance due to parasitic capacitance. The necessity of fill arises from the need to ensure planarization of dielectric layers by using chemical mechanical polishing. Without adequate fill, areas of the chip can suffer from uneven planarization.

If using fill is inevitable the first question to arise is how can designers minimize its impact? The design community has had to rely on intuitive answers as to what the impact actually is and consequently how to reduce it. It is axiomatic that regardless of the level of impact, if it can be accurately modeled, then successful designs incorporating fill can be built. In the absence of a quantitative way to assess the impact of fill, designers are working in the dark, and assuming unwanted risk.

3D Electromagnetic solvers simply are not up to rigorously solving for the hundreds of thousands of elements that are seen in filled inductor layouts. So naturally designers sought to eliminate fill from their designs. If fill is not present in the design then there is no need to accurately model it.

Nevertheless Lorentz Solution has run PeakView to rigorously solve test cases of limited size to learn more about metal fill impacts on inductor performance. A variety of fill shapes and structures were used. Even eddy currents inside of fill elements was looked at. One of the first things learned was that adding stacked vias to metal fill creates large capacitive coupling to the substrate. This is intuitive, as the ‘plate’ is effectively moved to the bottom metal, much closer to the substrate.

It is easy to comply with foundry rules for via fill without placing connecting vias in all the metal fill structures. Typically via fill density requirements are on the order of single digit percentages. So moving forward it was decided to focus exclusively on floating fill without inter-layer connections.

At low fill densities there is a minimal bottom place capacitance shift when the fill is fully floating. To come up with data concerning higher densities and with fill on all layers, as would be seen in production silicon, Lorentz concluded that the only reliable way to proceed is with silicon data.

Lorentzteamed up with Altera, TSMC and Mentor Graphics. Lorentz Solution designed inductors at 20nm and embedded them in test keys. A series of different fill shapes and densities were applied to the device under test. The silicon was fabricated and measured by TSMC, who generously agreed to assist in this effort. As the next step, Lorentz de-embedded the raw data and performed data analysis.

What made this project useful is that PeakView has a method for simulating metal fill that dramatically reduces the size of the problem. This feature is in PeakView’s CMP package. The CMP package, in addition to handling fill intelligently, automatically merges slotting and striping commonly found in wide metals. PeakView’s CMP Package can automatically identify metal fill in designs. This alleviates the need for a manual step prior to EM simulation to remove fill from the layout. Once the fill is identified, the user can choose to have the simulation ignore it, or have it modeled.

Silicon test chip data was used to show a good match with PeakView CMP results. The other valuable thing learned was that the fill densities and structures used had negligible impact on L and a very small impact on Q – and that was mostly from a slight addition to the parasitic capacitance.

With hard data showing that fill can have a low impact and that this impact can be properly modeled, designers should be much more comfortable using recommended fill densities in their designs. Now let’s analyze the potential benefits of using recommended fill.

When metal fill is used, the result is a more planar assembly of the dielectric and metal layers. The foundries provide detailed information on the process geometry in technology files that are used directly or indirectly in every aspect of the design flow. TSMC provides iRCX files and other foundries use ITF files for this purpose. Every tool that relies on this information relies on the fab producing silicon that conforms to the foundry specification. Simply put, using fill that is out of range can produce silicon stack up geometry that does not match the iRCX or ITF data provided. This exposes designers to an unforeseen risk because analysis tools may be working with input files that do not reflect what was fabricated.

It is well understood that without metal fill, inductors may be the source of moisture infiltration into the die. After moisture enters the chip, it can rapidly move to device junctions, causing catastrophic chip failure. Some foundries insist that seal rings be used when fill is reduced to avoid issues arising from dielectric damage.

Seal rings also take up room on the die, and do not always provide a significant beneficial design effect other than creating a moisture barrier. What if designers could remove seal rings? Suddenly it is looking like with the combination of stack up information integrity and area savings that fill might not be so undesirable.

In conclusion silicon data shows that when fill is properly designed its detrimental effect is not significant. Further, the extent of this effect can be simulated effectively by PeakView’s CMP Package. Lastly there appear to be good reasons to maintain the fill densities that are recommended around and underneath inductors.

The value of a thorough study of the effects of fill at 20nm has been shown useful in removing confusion regarding the role of fill in inductors at advanced process nodes.

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