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Granite River Labs and TSMC Expand Agreement

Granite River Labs and TSMC Expand Agreement
by Paul McLellan on 08-28-2014 at 7:01 am

For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to recover the huge capital investment a modern fab entails. With many SoCs having over a hundred IP blocks, getting the IP qualified is an essential part of a design team being able to get a design into production. Taking a systematic approach to IP quality is paramount for successful SoC products.

TSMC’s latest IP validation has multiple steps, increasingly expensive to execute but with increasing confidence level in the IP. The first 3 steps are a review of the IP without manufacturing it. The later steps involve running extensive tests on IP that has been manufactured, typically in a shuttle run for a new process that is not yet in volume production. For more mature processes where a lot of IP has been in use for many years, the sheer number of designs in successful volume production is its own guarantee of IP quality.


  • Physical review (DRC, LVS, ERC, antenna checks)
  • DFM compliance (DFM-LPE, LPC, dummy fill, VCMP)
  • Pre-silicon assessment (design kit review, design review)
  • Silicon assesment (tapeout review, silicon report review)
  • Split lot silicon assessment (split lot tapeout and report review)
  • IP Validation Center (audit IP testing results by TSMC test lab)
  • Volume production

    Last month, TSMC’s IP Validation Center and Granite River Labs deepened their relationship and further expanded the TSMC9000 IP validation ecosystem. This covers expanded test capacity, test auditing and posting IP validation results on TSMC-online. This is a part of item #6 above, leveraging the expertise of GRL in the test and validation of high speed interfaces.

    GRL will serve as an IP validation partner to TSMC. The test methodology development and correlation will be done at GRL’s office in Hsinchu (where TSMC is headquartered of course). The bulk of the work will be carried out at GRL in Santa Clara and Bangalore. TSMC will subcontract to GRL to create a test methodology for the specific PHY. GRL can then use their extensive expertise and wide range of costly equipment to perform the testing. The results will then be available through TSMC-online like where it can be searched by potential users.

    GRL has extensive electrical test facilities using Introspect, Teledyne Lecroy, Tektronix, Keysight and others. They also hav protocol test solutions that can handle error injection, stress testing, protocol exerciser automation and so on. They have R&D sites in Oregon and Japan. Labs in Santa Clara, Bangalore, Penang, Hsinchu and Taipei. The Asian HQ is in Singapore, worldwide HQ is in Silicon Valley.

    More articles by Paul McLellan…

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