Recently I published two blogs on Fully Depleted Silicon On Insulator (FDSOI) and the potential the technology shows for a variety of low power and wireless applications. In order to produce FDSOI devices, the device layer has to be thin enough to ensure the device is fully depleted and ideally the buried oxide has to be thin enough to allow back gate for performance tuning. Soitec has been the industry leader in developing the substrate technology for FDSOI and last Thursday I had the opportunity to discuss FDSOI substrates with Christophe Maleville, Executive Vice President of Digital Electronics Business Unit, Soitec.
Soitec’s proprietary process for FDSOI is Smart CutTM. The basic process is as follows:
The Smart CutTM process has been in use on 300mm wafers for 15 years. Originally the wafers had thicker device layers and were used to make Partially Depleted SOI (PDSOI) devices. The problem with PDSOI was that you had an expensive SOI substrate that still requiring all the same processing as a standard planar wafer, this relegated PDSOI to niche use. FDSOI still uses an expensive substrate but at the same time eliminates a lot of processing making it cost competitive with the alternative technologies.
Around 2004 or 2005 the industry was faced with the limitation of bulk planar technologies and realized that somewhere around the 20nm node the technology was going to reach its limit. The solution was to move to fully depleted devices with better electrostatic control. In order to successfully make FDSOI very good device layer thickness uniformity is required and at the time the uniformity being produced was approximately 5x what it needed to be. The industry began to pursue FinFETs on bulk to create fully depleted devices. Since that time Soitec has been able to achieve five angstrom uniformity making FDSOI a viable alternative to FinFETs.
In 2010 Soitec demonstrated they could meet the requirements for FDSOI and in 2012 ST-Ericsson demonstrated FDSOI devices. As noted in my previous blogs, ST is currently producing 28nm devices, Samsung is ramping 28nm devices, GLOBALFOUNDRIES will soon be ramping 22nm devices and 12nm is in development.
The following table summarizes FDSOI material requirements by node:
| class=”cms_table_grid_td” | Node
| class=”cms_table_grid_td” | Delivered device thickness (nm)
| class=”cms_table_grid_td” | Device thickness after processing (nm)
| class=”cms_table_grid_td” | Buried oxide thickness (nm)
| class=”cms_table_grid_td” | 28nm
| class=”cms_table_grid_td” | 12nm + or – 0.5nm
| class=”cms_table_grid_td” | 6nm
| class=”cms_table_grid_td” | 25nm
| class=”cms_table_grid_td” | 22nm
| class=”cms_table_grid_td” | 12nm + or – 0.5nm, improved roughness
| class=”cms_table_grid_td” | 5-6nm
| class=”cms_table_grid_td” | 20nm
| class=”cms_table_grid_td” | 12nm
| class=”cms_table_grid_td” | 12nm
| class=”cms_table_grid_td” | ~5nm
| class=”cms_table_grid_td” | 20nm, may go to 15nm for improved electrostatic control
| class=”cms_table_grid_td” | 7nm
| class=”cms_table_grid_td” | Add strain
| class=”cms_table_grid_td” | ~4nm
| class=”cms_table_grid_td” | TBD
The delivered device thickness is the thicknesses on the wafer delivered by Soitec. In the course of device fabrication, the device layer is thinned to the “after processing” thickness. After processing 5-6nm can be done today with high yield. Thinning below 4nm leads to very critical cleaning and epitaxial requirements.
Strain can be done by creating a strained silicon layer over a silicon germanium layers for the device layer. After bonding the germanium layer is removed during the splitting operation leaving a strained silicon layer over the buried oxide layer.
Soitec has been manufacturing 300mm PDSOI wafers (mainly for IBM, AMD and Freescale) as well as making other products such as Power and Photonics wafers. PDSOI had been in production since 2012 and Soitec is now converting the capacity to FDSOI and ramping up FDSOI production. Soitec has facilities in France and Singapore. In France capacity can be converted to FDSOI in 4 to 6 months and in Singapore in 6 to 9 months with a potential global capacity of 1.5 million wafers per year between the two sites. Soitec has also licensed Smart CutTM to two other companies.
FDSOI has demonstrated good analog and RF performance and very low power. ST-Ericsson have shown a 3GHz processor with very little temperature rise during operation making it ideal for integration near a heat sensitive devices. Due to the thin isolated device layer FDSOI has good soft error rate immunity and is roughly 1,000x more radiation tolerant than other dveices. With a 15nm buried oxide 0.35 volt operation has been demonstrated by LEAP in Japan.
FDSOI is well suited for 5G, wearables, IOT and smart watches and provides capabilities automotive needs now.