Introduction to Visualizer for the VHDL Users

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …

Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jun 30, 2020 3:00 PM - 4:00 PM US/Pacific Register Overview In this session we provide an in-depth overview of Mentor’s recently launched Symphony Mixed-Signal Platform. Symphony is the industry’s fastest and most configurable mixed-signal solution …

Introduction to Visualizer for the VHDL Users

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …

Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jun 30, 2020 3:00 PM - 4:00 PM US/Pacific Register Overview In this session we provide an in-depth overview of Mentor’s recently launched Symphony Mixed-Signal Platform. Symphony is the industry’s fastest and most configurable mixed-signal solution …

WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis

Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Designers must verify and characterize their IP’s sensitivity to random parametric variations in the manufacturing …

WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential features such as throughput, …

Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required functionality for your chip and …

Fluent Meshing in 15 Minutes: Automotive External Aero

June 30, 2020 11 AM EDT / 3 PM GMT Venue: Online Attend this webinar to learn how Ansys Fluent can accelerate the meshing and solve time for automotive external aerodynamics applications. There will be a live demonstration showcasing: CAD import to volume mesh generation User-friendly task-based workflows How to customize and save your workflow …

Teaching Sustainable Development to Students with Social Impact Audit Tool

June 30, 2020 11:00 AM (EDT) / 3:00 PM (GMT) Venue: Online Product design involves the choice of materials, the processes used to shape them, transport modes, characteristics of the way the product is used and of its disposal at end of life. All of these have environmental, economic and social implications. Environmental life cycle …

Accelerate Post-Processing with Ansys EnSight

June 30, 2020 11:30 AM (IST) Venue: Online Analyze, visualize and communicate your simulation data with Ansys EnSight. Engineers use this powerful, general purpose post-processing tool to gain new design insights and then clearly and effectively sell their recommendations. Flexible EnSight can read and visualize data from most simulation tools — including Ansys solutions and …

Tessent Visualizer – Increase your productivity with less time spent on DFT debug

Register For This Web Seminar Online - Jun 30, 2020 5:00 PM - 6:00 PM US/Pacific Register Online - Jul 1, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Designed for billion-gate designs, Tessent Visualizer is helping DFT engineers be more productive by addressing key challenges of the most time-consuming DFT debug tasks. Included …