Loading Events

« All Events

  • This event has passed.

Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs

June 30, 2020 @ 10:00 AM - 11:00 AM

graham allen 1600x960.jpg.imgw .850.x

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required functionality for your chip and deliver competitive products to market faster. Register now to learn about:

  • High-performance computing market trends impacting SoC designs from a senior executives in the IP business unit
  • Use cases and optimized IP solutions for AI, hyperscale data center, and networking applications
  • Meeting your evolving high-performance computing design requirements with a comprehensive IP portfolio including USR/XSR &HBI die-to-die, DDR5, HBM2/2E, PCIe 5.0, & CXL

Product Expert Speaker: Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

Graham Allan brings over 25 years of experience in the memory industry. Graham has spoken at numerous industry conferences and is a significant contributor to the SDRAM, DDR and DDR2 JEDEC memory standards. He currently holds 25 issued patents in the area of memory design.

Gary Ruggles, Sr. Product Manager

Product Expert Speaker: Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs

Gary Ruggles brings over 25 years of experience in electronics and integrated circuit design. Gary began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University, where he taught courses in Solid State Physics and VLSI Processing.

Share this post via:


June 30, 2020
10:00 AM - 11:00 AM