FPGA/ASIC/SOC design
High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential features such as throughput, …
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Powering the Next-Generation Machine Learning Solution with Graph Analytics on Connected Data with Xilinx and TigerGraph
Please join Xilinx and TigerGraph to learn about the next-generation machine learning solution combining cutting edge hardware with graph analytics on connected data to answer these key questions: How do I understand the wellness journey of a patient and find patients like them in real-time to figure out the recommended next steps? Can I understand a customer’s …
7 Tips in 17 Minutes: Previewing the All-New Ansys Discovery
The all-new Ansys Discovery provides engineers with a user-friendly, fast and powerful 3D simulation tool that helps enable the conceptualization, evaluation and refinement of next generation products. Attend this webinar to learn: How Discovery will increase the speed and accuracy of your design Diverse physics Key features of Discovery’s new user interface How to achieve …
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2020 CASPA Tech Education Day
2020 CASPA Tech Education Day HiFive from SiFive: Project Show Case Venue: Zoom Video Webinar Date: Saturday, Aug.15, 2020 Time: 4:00pm – 6:00pm PDT Registration Link: https://www.eventbrite.com/e/2020-caspa-and-sifive-special-education-day-event-tickets-113575328866 Special announcement: 1. Please join our Telegram group: https://t.me/CASPAEDU 2. There are 10 Hifive boards as gifts to give away, and you must register to win. Gifts will be shipped to US …
AI SoC Case Study: Emerging Neural Networks Drive IP Innovation
The demand for neural network processing is requiring SoC hardware innovation across all market segments. These demands bring a new set of IP requirements unique to different segments, including new processors, higher bandwidth memories, high speed interconnect, and optimized architectural configurations. Constantly evolving next-generation neural networks place unique additional demands over and above the standard …
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Riscure Hybrid Workshop 2020 – Embedded Security via Webcasting & Offline
Welcome to the two (2) day, 13th Annual Hybrid Riscure workshop on September 3 & 4th 2020. The event is will focus on topics relevant to embedded security. The delivery of the event will be webcast live to the public via registered attendees only and will have a private by invite only offline workshop (max …
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How FPGAs Enable Industrial Automation and Transformation to Industry 4.0
As Industry 4.0 becomes more pervasive, and factories transform to become Smart and Connected, new architectures emerge, paving the way for new industrial applications. Field devices are embedding intelligence and in many cases, cloud connectivity is being integrated. This webinar will present an overview of current trends in the Industrial market and highlight the role …
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Free webinar – Image sensor testing and packaging
Is an image sensor your next development project? Invest 45 minutes in company of The capabilities of Center of Applied Photonics and Presto Engineering and hear how we can test your sensor. Agenda for the webinar: Level of testing, at which level are we testing image sensors Test Standards, What are the standards for testing …
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Chips Alliance Workshop
The CHIPS Alliance is an organization which develops and hosts high quality, open source hardware code (IP cores), interconnect IP (phy and logical protocols), and open source software development tools for design, verification, and more. We seek to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The …
The Edge Event 2020
The Edge Event will gather 1000+ enterprises, telcos, data centre operators, cloud service providers, analysts and array of edge and IoT solution providers all looking to claim their place at the edge. We have been continuously reviewing the best way to serve our edge computing community over the past couple of months. As the global situation with COVID-19 continues …
DVCON Europe 2020
Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.
Webinar on System Development Using Agnisys
In this webinar we present the Agnisys way of developing embedded products. This provides a path that avoids many pitfalls present in a typical flow, such as a slow process, duplicate efforts, wasteful resources, and so on. Generate code directly from specification using best-in-class Agnisys products and innovative tool flow. The Agnisys flow involves the …
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