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High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
August 4, 2020 @ 10:00 AM - 11:00 AM
If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential features such as throughput, power-efficiency, reach, and latency. In case of die-to-die, several more considerations must go into your IP selection criteria based on the target packaging configuration.
Attend this webinar to learn about use cases for long reach connectivity in SoCs and ultra-short reach die-to-die connectivity in multi-chip modules and essential considerations such as data throughput or bandwidth, energy efficiency, latency, reach, and overall integration when choosing PHY IP for 56G/112G Ethernet and die-to-die connectivity.
PRESENTERS: Manmeet Walia, Senior Product Manager for Mixed-Signal PHY IP and Manuel Mota, Product Marketing Manager for DesignWare Data Converter, High-Speed SerDes, and Bluetooth IP Manmeet Walia is a Senior Product Manager for Mixed-Signal PHY IP at Synopsys. He brings more than 18 years of experience in product marketing, product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications.
Manuel Mota joined Synopsys in 2009 as a Product Marketing Manager and is responsible for the DesignWare Data Converter, High-Speed SerDes, and Bluetooth IP product lines. He brings more than 18 years of technical and marketing experience to his position. Webinar Organizers: SemiWiki.com and Synopsys