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Q2FY24TessentAI 800X100 
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Siemens EDA
Posted on by Daniel Nenni

Semiconductor Design: Chips to Systems!

Semiconductor Design: Chips to Systems!
by Daniel Nenni on 01-12-2015 at 8:00 pm
Categories: EDA, Events, Siemens EDA

This is the 20[SUP]th[/SUP] year of DesignCon and I’m really looking forward to it. While I haven’t attended all 20 I certainly have attended the majority of them. Now it is like a college reunion for me seeing all sorts of friends and former coworkers. One of them is even a keynote but more on that later. This year there are 14 conference tracks covering semiconductor design through to the system level with more than 100 sessions, panels, and tutorials. Take a look HERE for the conference overview.

My good friends at Mentor Graphics are a platinum sponsor this year with Technical Workshops on:

  • DDR Interface and SerDes Channel Design for High Performance FPGA – based PCBs
  • Electromagnetic Simulation for Electronic Systems
  • Designing Manufacturable Stackups – A Comprehensive Approach to Stackup and SI Modeling
  • A Holistic Approach to IC, Package and Board co-optimization
  • DDR4 Board Design and Signal Integrity Verification Challenges
  • Accurate statistical analysis of SERDES links considering correlated input patterns, data-dependent edge transitions, and transmit jitter

Mentor Graphics® is the worldwide market leader in PCB systems design and analysis technologies. Mentor Graphics will be showcasing its advanced HyperLynx and Nimbic technologies for electrical sign-off, including a complete analysis environment for DDRx designs, multi-gbps channel analysis, full-wave 3D electromagnetic modeling, and power distribution design. Visit booth #935 to learn more about Mentor’s technologies and best practices for virtual prototyping or by attending Mentor Graphics technical presentations.

You can also visit their booth and spend some quality time with experts in the field of signal and power integrity analysis, IC/package/board co-optimization, and automatic stack-up design.

Here are the conference tracks that cover all aspects of chip, board, and system design:

[LIST=1]

  • Optimize Chip-Level Designs for Signal and Power Integrity
  • Overcome Analog and Mixed-Signal Modeling and Simulation Challenges
  • Wireless and Photonic Integration
  • System Co-Design: Chip/Package/Board: Modeling and Simulation
  • Characterize PCB Materials and Processing Characterization
  • Apply PCB Design Tools
  • Design Parallel and Memory Interfaces
  • Optimize High-Speed Serial Design
  • Detect and Mitigate Jitter, Crosstalk, and Noise
  • Leverage High-Speed Signal Processing for Equalization and Coding
  • Ensure Power Integrity in Power Distribution Networks
  • Achieve Electromagnetic Compatibility and Mitigate Interference
  • Apply Test and Measurement Methodology
  • Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques

    This year there are insightful keynotes on Tuesday, Wednesday, and Thursday by industry luminaries:

    [LIST=1]

  • Thomas H. Lee Ph.D, Professor of Electrical Engineering, Stanford University
  • Karen Bartleson, Senior Director of Corporate Programs and Initiatives, Synopsys
  • Alex Lidow Ph.D, CEO, Co-Founder, Efficient Power Conversion Corporation

    Karen is the friend I mentioned. She is very active with IEEE and is currently a candidate for IEEE president! Congratulations Karen! I will be at DesignCon all three days and it would be a pleasure to meet you!

    Taking place annually in Silicon Valley, DesignCon was created by engineers for engineers and remains the largest gathering of chip, board and systems designers in the country. Combining technical paper sessions, tutorials, industry panels, product demos and exhibits, DesignCon brings engineers the latest theories, methodologies, techniques, applications and demonstrations on PCB design tools, power and signal integrity, jitter and crosstalk, high-speed serial design, test and measurement tools, parallel and memory interface design, ICs, semiconductor components and more.

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