Webinar: Verisium Debug for UPF Low Power Design

Date: Tuesday, June 20, 2023

Time: 11:00am PDT | 2:00pm EDT | 7:00pm CET

Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs.

What you will learn

• Understand features available in Verisium Debug
• ​Learn about the low-power debug capabilities available in Verisium Debug
• Learn how to debug UPF low-power designs with Verisium Debug

Who should attend 

• Design engineers
• Verification engineers
• CAD engineers

REGISTER HERE