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Webinar Series: Thinking Outside the Chip

June 23, 2020

Whether by talent, art, or black magic, designing RF circuitry is one of the most challenging engineering tasks there is. RF engineers confront a myriad of challenges to bring their designs to life.  From the ability to verify a complex 5G standard; running electromagnetic (EM) analysis across chip, package, and board boundaries; or even simply needing to verify RF module connectivity and a manufacturing flow you can trust, these challenges can overwhelm the traditional EDA design flows that are notoriously fragmented by using multiple vendors.

Learn how to overcome challenges in designing RFIC, RF, and RF SiP modules through this three-day webinar series:

Choose your session time and date when registering

Overcome RFIC and RF Module Implementation Challenges

June 23, 2020 – 8:00 am PDT/11:00 am EDT and 3:00 pm PDT/6:00 pm EDT

Implementation of RF SiP or modules is plagued with mistakes resulting from using disjointed design tools across multiple design teams. IC design teams use one implementation platform, and the SiP team uses another. If the RF module contains acoustic filters or MMIC, it will usually require yet another design platform. Solving a relatively “simple” problem, like verifying connectivity (LVS) and ensuring a designer aligns the bump pads or connects bond wires correctly, is proving to be challenging. Learn about module implementation challenges and a comprehensive solution to streamline manufacturing using the Cadence® Virtuoso® design platform and Allegro® interoperability, including:

· Schematic-driven SiP implementation flow

· RFIC and RF module co-design environment for simultaneous editing across chip, module, and package designs

· Streamline manufacturing solution

Every dB Counts: Reduce Errors with Integrated EM Modeling and Analysis

June 24, 2020 – 8:00 am PDT/11:00 am EDT and 3:00 pm PDT/6:00 pm EDT

RF engineers continually analyze and optimize their RF circuits and are in constant pursuit of increasing EM analysis fidelity. When designing mmWave IC or RF modules, every metal trace in the signal path must be modeled using a variety of EM technologies. The process of selecting and setting up layout to be analyzed, defining and setting up EM solvers, and integrating EM models back into circuit simulation is a manual and error-prone task. Explore the challenges of running EM simulations and automating the back-annotation task to reduce human error. We also will demonstrate how EM tools are integrated into the Virtuoso design platform to make an efficient EM modeling flow.

Learn about:

· Saving time and speeding up design work with smart integrated EM solvers, which automate hours of manual work required to run critical passive components and interconnects

· Finite element method (FEM) and method of moment (MoM) solvers to choose the best EM solver for your design

Simulate 5G Signal Sources for Complete Signoff Verification

July 2, 2020 – 8:00 am PDT/11:00 am EDT and 3:00 pm PDT/6:00 pm EDT

What do 400MHz bandwidth, 20Gbps data rates, and 28GHz mmWave technology all have in common? They are but a few of the minimum specifications for 5G chipsets. Being able to simulate and verify these mammoth chips requires new design techniques and new EDA tools to support all of the engineering tasks involved. The webinar places an emphasis on the Spectre® 5G signal source and the methodologies for setting, tracking, and verifying the multitude of simulation requirements in modern communication and sensing systems. Learn about:

· Cadence’s comprehensive RF simulation environment and analysis capabilities

· Verifying the growing complexities and simulation needs of 5G, LTE, automotive, and other complex RF systems.

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