Webinar Series AI Architecture to Silicon Yield

Technology Update: Designing AI Silicon with Stratus HLS

Wednesday, September 9, 2020
14:00 BST / 15:00 CEST / 16:00 EEST/IDT / 10:00am ET

Speaker: Dave Apte

When designing ultra-low power artificial intelligence (AI) and machine learning (ML) applications such as local inferencing on battery-powered edge devices, custom silicon tailored to the application is usually the optimal approach.

During this live webinar you will learn from Cadence experts how engineers worldwide are leveraging new features in Stratus™  High-Level Synthesis (HLS) to help find and implement the most effective silicon for these demanding AI edge applications.

Agenda:

• Why is Stratus HLS being used to design AI /ML hardware?

• New Stratus features supporting AI design

• Demonstration

• Q&A