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Webinar: How to Exhaustively Verify that Your Custom Instructions Aren’t Secretly Breaking Your RISC-V Design

October 24, 2023 @ 8:00 AM - 9:00 AM

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Title: How to Exhaustively Verify that Your Custom Instructions Aren’t Secretly Breaking Your RISC-V Design

Date: Tuesday, October 24, 2023

Time: 8:00 AM Pacific Daylight Time

Duration: 1 hour



The last thing you want to do when adding custom instructions to your RISC-V design is to unintentionally insert some deep corner case bug – the kind of bug that’s discovered by your customers a month after the end-product has shipped.

Simulation-based verification approaches find many common errors; but to be really sure that there are no hidden side-effects or “specification bugs”, an exhaustive, formal-based verification flow is also needed.

In this presentation we will guide you through the simple design and verification steps you can take to combine simulation and formal approaches; with a particular emphasis on leveraging automated, formal-based sequential equivalence checking (SLEC). These methodologies will be illustrated with real-world case studies.

This is a joint webinar with Codasip – a Custom Compute and
RISC-V leader.

What You Will Learn:

  • RISC-V customization principles
  • An efficient design automation and customization flow for RISC-V processors
    • Processor design in a high-level description language
    • Going from high-level description language to RTL generation
  • A light-weight formal verification flow targeted towards customization

Who Should Attend:

  • Design engineers
  • Design verification engineers
  • Formal verification engineers
  • Verification managers
  • RISC-V enthusiasts

What/Which Products are Covered:

  • Codasip Studio design automation toolset
  • Codasip CodAL processor description language
  • Codasip L31 RISC-V embedded processor
  • Siemens Questa OneSpin Processor Verification App
  • Siemens Questa OneSpin Equivalent RTL (SLEC)


Sven Beyer

Sven Beyer
Program Manager, Processor Verification
Siemens EDA

Sven Beyer is the Program Manager for Formal Processor Verification at Siemens EDA (Siemens Digital Industries Software). Sven has close to twenty years of experience in formal verification, with a specific focus on industrial processor verification. Prior to Siemens EDA, he was with OneSpin Solutions since its inception, filling various roles involving methodology, application, and product management. He has been instrumental to the development of many formal verification IPs and apps and holds several patents, including one for processor verification. Sven holds a Dr.-Ing. (equivalent to a PhD) in formal verification from Saarland University, Germany.

Laurent Arditi

Laurent Arditi
Formal Verification Lead

Laurent Arditi has 25+ years of experience in the semiconductor industry. He holds a Ph.D. in formal verification from the University of Nice, and did a postdoc at Stanford University. He worked for Texas Instruments as a modeling engineer, then for a startup Esterel Technologies, working on high-level synthesis. After this, Laurent worked for 16 years at Arm, leading a formal verification team and applying formal methods to validate CPUs. He now drives the development of formal verification at Codasip.

Zdenek Prikryl

Zdenek Prikryl

Zdenek Prikryl, the CTO of Codasip, has over 20 years of experience in processor design, including general-purpose and application-specific instruction set processor designs, from small and simple MCUs, RISCs, to highly complex DSPs/VLIWs. Zdeněk has been also involved in embedded software and hardware systems design, and driving R&D activities for many years. He created and introduced the technology and methodology used in Codasip’s unique processor design tools and RISC-V processor IPs.


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October 24, 2023
8:00 AM - 9:00 AM
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Siemens EDA