SemiWiki WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

As the new portable stimulus standard reaches broader deployment, different uses are emerging to take advantage of the capabilities inherent in this format. This can now be extended beyond test and into verification, prototyping, and more.

What You Will Learn

This webinar will discuss Test Suite Synthesis, where verification scenario intent is described using the new Portable Stimulus Standard (PSS) and then synthesized to the respective process implementation. The white box intent description can be used to accelerate UVM block verification, Software Driven Verification (SDV) for SoCs, and prototyping and post-silicon validation. This increases design quality while reducing schedules. In addition, this same test description can be used across all these processes, providing a continuous, back and forth flow across the entire verification process. During the webinar you will see a demonstration of the practical application of test suite synthesis on real designs as they progress from architecture to block to SoC, leveraging hybrid verification techniques.

Who Should Attend

• Test engineers and managers
• Verification engineers and managers
• Those working on SoC prototyping
• Those working on post-silicon validation