Webinar: An Intelligent System Design Platform for Chiplet-Based Architectures

Date and Time

Wednesday, May 27, 2020
Time: 10:00am – 11:00am (PDT)

Providing the best alternative to advanced monolithic SoCs, multi-chiplet packages have become a very attractive option for the next generation of cost-sensitive designs. However, as many engineers begin to realize the benefits of a multi-chiplet packaging approach, including 3D stacking, they are struggling to grasp what changes are needed to their design flows.

To address the challenges of this More Than Moore trend, Cadence has adopted the Intelligent System Design™ strategy, driving the development of new tools and flows that reach beyond the single-chip domain. Please join us in this one-hour webinar with live Q&A from our panel of experts, who will discuss some of the benefits and challenges of designing heterogeneously integrated packages and outline the requirements for developing a modernized design flow for today’s multi-chiplet architectures.

Topics that will also be covered are:

· System-level design aggregation and connectivity

· Chiplet/package co-design

· Multi-chiplet layout requirements

· Cross-domain electrical/thermal modeling

Cadence Experts

· Art Schaldenbrand, Circuit Simulation

· Brad Griffin, Signal Integrity/Power Delivery

· CT Kao, Electrothermal Analysis

· Dan Baldwin, Advanced Packaging

· Jerry Zhao, EM-IR, 3DEM

· John Park, Cross-Platform Design

· Yuval Shay, Analog IC Design